12. Traps

In RISC-V terminology, a trap is the mechanism that handles interrupts and exceptions. The difference between an exception and an interrupt is that an exception is synchronous: For example, it can be by an invalid instruction executed by the core. On the other hand, an interrupt is caused by an external event. For example, an interrupt can be activated by a timer.

Upon a trap, the following things happen:

The reason for the trap is stored in the mcause CSR
The address of the instruction that was interrupted by the trap is stored in the mepc CSR
If there is extra information for the specific trap, it is stored in mtval, else it is set to 0
The MPIE field of mstatus is set to MIE
The MIE field of mstatus is set to 0
The pc is set to mtvec (in direct mode or for exceptions) or to mtvec + 4 * cause if the mode is vectored and the cause is an interrupt

The privileged part of the RISC-V docs also define some instructions. One of them is MRET, which return from a trap handler and does the following:

It resets mstatus.MIE to mstatus.MPIE
It sets mstatus.MPIE to 1
It sets pc to mepc

The other instruction that is defined in the privileged part of the ISA is the WFI (wait for interrupt). It should halt the processor until an interrupt occurs. However, this instruction is only meant to save power; a legal implemention is a NOP.

Let's do the easy work first and implement WFI as a NOP for now.

src/core/decode_write.vhd CHANGED Viewed

@@ -343,6 +343,8 @@ begin
 					else
 						v_decode_output.is_invalid := '1';
 					end if;
 				elsif opcode = "1111111" and funct3 = "000" then
 					-- LED (custom instruction): set the LEDs to the 8 least significant bits of rs1
 					v_decode_output.operation := OP_LED;

 					else
 						v_decode_output.is_invalid := '1';
 					end if;
+				elsif funct7 = "0001000" and rs2 = "00101" and opcode = "1110011" then
+					-- WFI (implemented as NOP)
 				elsif opcode = "1111111" and funct3 = "000" then
 					-- LED (custom instruction): set the LEDs to the 8 least significant bits of rs1
 					v_decode_output.operation := OP_LED;

Now let's implement MRET, which is also quite easy.

src/core/decode_write.vhd CHANGED Viewed

@@ -300,6 +300,9 @@ begin
 					-- ECALL
 				elsif i_imm = "000000000001" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- EBREAK
 				elsif opcode = "1110011" then
 					v_decode_output.operand2 := "00000000000000000000" & i_imm;  -- store CSR register in operand 2
 					v_decode_output.destination_reg := rd;

 					-- ECALL
 				elsif i_imm = "000000000001" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- EBREAK
+				elsif funct7 = "0011000" and rs2 = "00010" and rs1 = "00000" and rd = "00000" and opcode = "1110011" then
+					-- MRET
+					v_decode_output.operation := OP_MRET;
 				elsif opcode = "1110011" then
 					v_decode_output.operand2 := "00000000000000000000" & i_imm;  -- store CSR register in operand 2
 					v_decode_output.destination_reg := rd;

src/core/execute.vhd CHANGED Viewed

@@ -310,6 +310,11 @@ begin
 					else
 						-- TODO: exception; trying to write to non-existent or read-only CSR
 					end if;
 				elsif input.operation = OP_LED then
 					led <= input.operand1(7 downto 0);
 				else

 					else
 						-- TODO: exception; trying to write to non-existent or read-only CSR
 					end if;
+				elsif input.operation = OP_MRET then
+					mstatus_mie <= mstatus_mpie;
+					mstatus_mpie <= '1';
+					v_jump := '1';
+					v_jump_address := mepc & "00";
 				elsif input.operation = OP_LED then
 					led <= input.operand1(7 downto 0);
 				else

src/core/types.vhd CHANGED Viewed

@@ -32,6 +32,7 @@ package core_types is
 		OP_CSRRW,
 		OP_CSRRS,
 		OP_CSRRC,
 		OP_LED
 	);

 		OP_CSRRW,
 		OP_CSRRS,
 		OP_CSRRC,
+		OP_MRET,
 		OP_LED
 	);

Now we'll consider exceptions. The following exceptions are defined: 0. Instruction address misaligned: generated on a taken branch or unconditional jump when the target address is not aligned

Instruction access fault: generated when the instruction fetch tries to fetch from a memory region that is not accessible
Illegal instruction: when decoding an instruction fails
Breakpoint: TODO
Load address misaligned
Load access fault
Store address misaligned
Store access fault ...
Environment call from M-mode

There are a lot more exceptions defined, but they are not applicable. Regarding interrupts, there are 3 that are potentionally interesting:

Machine system interrupt
Machine timer interrupt
Machine external interrupt

The machine system interrupt is caused by other cores. Since our implementation only has one core, it is not applicable. The machine external interrupt is caused by peripherals, but at this point we don't have them, so we can ignore this interrupt as well. So only the machine timer interrupt is left, and I will postpone the implementation of this to a later lesson.

First, I'll set up the basic structure of how traps work.

...

src/constants.vhd CHANGED Viewed

@@ -1,5 +1,6 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use work.types.all;
@@ -16,4 +17,8 @@ package constants is
 		active => '0',
 		address => (others => '0')
 	);
 end package constants;

 library ieee;
 use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use work.types.all;
 		active => '0',
 		address => (others => '0')
 	);
+	constant MEM_ADDRESS_BITS: integer := 14;
+	constant MEM_ADDRESS_MIN: std_logic_vector(31 downto 0) := (others => '0');
+	constant MEM_ADDRESS_MAX: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned((2**MEM_ADDRESS_BITS) - 1, 32));
 end package constants;

src/core/constants.vhd CHANGED Viewed

@@ -14,12 +14,14 @@ package core_constants is
 	constant DEFAULT_DECODE_OUTPUT: decode_output_t := (
 		is_active => '0',
 		is_invalid => '0',
 		operation => OP_ADD,
 		operand1 => (others => '0'),
 		operand2 => (others => '0'),
 		operand3 => (others => '0'),
 		destination_reg => (others => '0'),
-		csr_read_only => '0'
 	);
 	constant DEFAULT_EXECUTE_OUTPUT: execute_output_t := (
@@ -77,4 +79,14 @@ package core_constants is
 	constant MCONFIGPTR_VALUE: std_logic_vector(31 downto 0) := X"00000000";
 	constant MISA_VALUE: std_logic_vector(31 downto 0) := X"40000100";  -- 32-bit RVI
 end package core_constants;

 	constant DEFAULT_DECODE_OUTPUT: decode_output_t := (
 		is_active => '0',
 		is_invalid => '0',
+		is_invalid_address => '0',
 		operation => OP_ADD,
 		operand1 => (others => '0'),
 		operand2 => (others => '0'),
 		operand3 => (others => '0'),
 		destination_reg => (others => '0'),
+		csr_read_only => '0',
+		pc => (others => '0')
 	);
 	constant DEFAULT_EXECUTE_OUTPUT: execute_output_t := (
 	constant MCONFIGPTR_VALUE: std_logic_vector(31 downto 0) := X"00000000";
 	constant MISA_VALUE: std_logic_vector(31 downto 0) := X"40000100";  -- 32-bit RVI
+	constant EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0000";
+	constant EX_CAUSE_INSTRUCTION_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0001";
+	constant EX_CAUSE_ILLEGAL_INSTRUCTION: std_logic_vector(3 downto 0) := "0010";
+	constant EX_CAUSE_BREAKPOINT: std_logic_vector(3 downto 0) := "0011";
+	constant EX_CAUSE_LOAD_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0100";
+	constant EX_CAUSE_LOAD_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0101";
+	constant EX_CAUSE_STORE_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0110";
+	constant EX_CAUSE_STORE_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0111";
+	constant EX_CAUSE_ENVIRONMENT_CALL: std_logic_vector(3 downto 0) := "1011";
 end package core_constants;

src/core/decode_write.vhd CHANGED Viewed

@@ -2,6 +2,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.core_types.all;
 use work.core_constants.all;
@@ -116,9 +119,11 @@ begin
 			if decode_input.is_active = '1' then
 				v_decode_output.is_active := '1';
-				v_decode_output.is_invalid := '0';
-				if opcode = "0110111" then
 					-- LUI
 					v_decode_output.operation := OP_ADD;
 					v_decode_output.operand1 := (others => '0');
@@ -298,8 +303,10 @@ begin
 					-- FENCE (implemented as NOP)
 				elsif i_imm = "000000000000" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- ECALL
 				elsif i_imm = "000000000001" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- EBREAK
 				elsif funct7 = "0011000" and rs2 = "00010" and rs1 = "00000" and rd = "00000" and opcode = "1110011" then
 					-- MRET
 					v_decode_output.operation := OP_MRET;

 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.types.all;
+use work.constants.all;
 use work.core_types.all;
 use work.core_constants.all;
 			if decode_input.is_active = '1' then
 				v_decode_output.is_active := '1';
+				v_decode_output.pc := decode_input.pc;
+				if not (MEM_ADDRESS_MIN <= decode_input.pc and decode_input.pc <= MEM_ADDRESS_MAX) then
+					v_decode_output.is_invalid_address := '1';
+				elsif opcode = "0110111" then
 					-- LUI
 					v_decode_output.operation := OP_ADD;
 					v_decode_output.operand1 := (others => '0');
 					-- FENCE (implemented as NOP)
 				elsif i_imm = "000000000000" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- ECALL
+					v_decode_output.operation := OP_ECALL;
 				elsif i_imm = "000000000001" and rs1 = "00000" and funct3 = "000" and rd = "00000" and opcode = "1110011" then
 					-- EBREAK
+					v_decode_output.operation := OP_EBREAK;
 				elsif funct7 = "0011000" and rs2 = "00010" and rs1 = "00000" and rd = "00000" and opcode = "1110011" then
 					-- MRET
 					v_decode_output.operation := OP_MRET;

src/core/execute.vhd CHANGED Viewed

@@ -31,7 +31,7 @@ architecture rtl of execute is
 	signal mscratch: std_logic_vector(31 downto 0) := (others => '0');
 	signal mepc: std_logic_vector(29 downto 0) := (others => '0');
 	signal mcause_int: std_logic := '0';
-	signal mcause_code: std_logic_vector(5 downto 0) := (others => '0');
 	signal mtval: std_logic_vector(31 downto 0) := (others => '0');
 	signal mip: std_logic_vector(15 downto 0) := (others => '0');
 	signal mcycle: std_logic_vector(31 downto 0) := (others => '0');
@@ -46,12 +46,22 @@ begin
 		variable v_jump: std_logic;
 		variable v_jump_address: std_logic_vector(31 downto 0);
 		variable v_mem_req: mem_req_t;
-		variable v_mcycle_next, v_mcycleh_next: std_logic_vector(31 downto 0);
-		variable v_minstret_next, v_minstreth_next: std_logic_vector(31 downto 0);
 		variable csr_set_bits, csr_clear_bits: std_logic_vector(31 downto 0);
 		variable v_temp: unsigned(63 downto 0);
 	begin
 		if rising_edge(clk) then
 			v_output := DEFAULT_EXECUTE_OUTPUT;
@@ -61,281 +71,370 @@ begin
 			v_jump_address := (others => '0');
 			v_temp := unsigned(mcycleh & mcycle) + 1;
-			v_mcycle_next := std_logic_vector(v_temp(31 downto 0));
-			v_mcycleh_next := std_logic_vector(v_temp(63 downto 32));
 			v_temp := unsigned(minstreth & minstret);
 			if instr_retire = '1' then
 				v_temp := v_temp + 1;
 			end if;
-			v_minstret_next := std_logic_vector(v_temp(31 downto 0));
-			v_minstreth_next := std_logic_vector(v_temp(63 downto 32));
-			if input.is_active = '1' and input.is_invalid = '0' then
-				if input.operation = OP_ADD then
-					v_output.result := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
-				elsif input.operation = OP_SUB then
-					v_output.result := std_logic_vector(unsigned(input.operand1) - unsigned(input.operand2));
-				elsif input.operation = OP_SLT then
-					if signed(input.operand1) < signed(input.operand2) then
-						v_output.result := std_logic_vector(to_unsigned(1, 32));
-					else
-						v_output.result := (others => '0');
-					end if;
-				elsif input.operation = OP_SLTU then
-					if unsigned(input.operand1) < unsigned(input.operand2) then
-						v_output.result := std_logic_vector(to_unsigned(1, 32));
-					else
-						v_output.result := (others => '0');
-					end if;
-				elsif input.operation = OP_XOR then
-					v_output.result := input.operand1 xor input.operand2;
-				elsif input.operation = OP_OR then
-					v_output.result := input.operand1 or input.operand2;
-				elsif input.operation = OP_AND then
-					v_output.result := input.operand1 and input.operand2;
-				elsif input.operation = OP_SLL then
-					v_output.result := input.operand1;
-					if input.operand2(4) = '1' then
-						v_output.result := v_output.result(15 downto 0) & "0000000000000000";
-					end if;
-					if input.operand2(3) = '1' then
-						v_output.result := v_output.result(23 downto 0) & "00000000";
-					end if;
-					if input.operand2(2) = '1' then
-						v_output.result := v_output.result(27 downto 0) & "0000";
-					end if;
-					if input.operand2(1) = '1' then
-						v_output.result := v_output.result(29 downto 0) & "00";
-					end if;
-					if input.operand2(0) = '1' then
-						v_output.result := v_output.result(30 downto 0) & "0";
-					end if;
-				elsif input.operation = OP_SRL or input.operation = OP_SRA then
-					v_output.result := input.operand1;
-					if input.operation = OP_SRL then
-						v_sign := (others => '0');
-					else
-						v_sign := (others => input.operand1(31));
-					end if;
-					if input.operand2(4) = '1' then
-						v_output.result := v_sign(15 downto 0) & v_output.result(31 downto 16);
-					end if;
-					if input.operand2(3) = '1' then
-						v_output.result := v_sign(7 downto 0) & v_output.result(31 downto 8);
-					end if;
-					if input.operand2(2) = '1' then
-						v_output.result := v_sign(3 downto 0) & v_output.result(31 downto 4);
-					end if;
-					if input.operand2(1) = '1' then
-						v_output.result := v_sign(2 downto 0) & v_output.result(31 downto 3);
-					end if;
-					if input.operand2(0) = '1' then
-						v_output.result := v_sign(1 downto 0) & v_output.result(31 downto 2);
-					end if;
-				elsif input.operation = OP_JAL then
-					v_jump := '1';
-					v_jump_address := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
-					v_output.result := input.operand3;
-				elsif input.operation = OP_BEQ then
-					if input.operand1 = input.operand2 then
-						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_BNE then
-					if input.operand1 /= input.operand2 then
-						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_BLT then
-					if signed(input.operand1) < signed(input.operand2) then
-						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_BGE then
-					if signed(input.operand1) >= signed(input.operand2) then
-						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_BLTU then
-					if unsigned(input.operand1) < unsigned(input.operand2) then
-						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_BGEU then
-					if unsigned(input.operand1) >= unsigned(input.operand2) then
 						v_jump := '1';
-						v_jump_address := input.operand3;
-					end if;
-				elsif input.operation = OP_SB then
-					v_mem_req.active := '1';
-					v_mem_req.address := input.operand1;
-					if input.operand1(1 downto 0) = "00" then
-						v_mem_req.value := x"000000" & input.operand2(7 downto 0);
-						v_mem_req.write_enable := "0001";
-					elsif input.operand1(1 downto 0) = "01" then
-						v_mem_req.value := x"0000" & input.operand2(7 downto 0) & x"00";
-						v_mem_req.write_enable := "0010";
-					elsif input.operand1(1 downto 0) = "10" then
-						v_mem_req.value := x"00" & input.operand2(7 downto 0) & x"0000";
-						v_mem_req.write_enable := "0100";
-					else
-						v_mem_req.value := input.operand2(7 downto 0) & x"000000";
-						v_mem_req.write_enable := "1000";
-					end if;
-				elsif input.operation = OP_SH then
-					-- TODO: a misaligned store should generate an exception
-					v_mem_req.active := '1';
-					v_mem_req.address := input.operand1;
-					if input.operand1(1 downto 0) = "00" then
-						v_mem_req.value := x"0000" & input.operand2(15 downto 0);
-						v_mem_req.write_enable := "0011";
-					else
-						v_mem_req.value := input.operand2(15 downto 0) & x"0000";
-						v_mem_req.write_enable := "1100";
-					end if;
-				elsif input.operation = OP_SW then
-					-- TODO: a misaligned store should generate an exception
-					v_mem_req.active := '1';
-					v_mem_req.write_enable := "1111";
-					v_mem_req.address := input.operand1;
-					v_mem_req.value := input.operand2;
-				elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or
-				      input.operation = OP_LBU or input.operation = OP_LHU then
-					-- TODO: a misaligned load should generate an exception
-					v_output.use_mem := '1';
-					v_output.mem_addr := input.operand1(1 downto 0);
-					v_mem_req.active := '1';
-					v_mem_req.address := input.operand1;
-					if input.operation = OP_LB or input.operation = OP_LH then
-						v_output.mem_sign_extend := '1';
-					end if;
-					if input.operation = OP_LB or input.operation = OP_LBU then
-						v_output.mem_size := SIZE_BYTE;
-					elsif input.operation = OP_LH or input.operation = OP_LHU then
-						v_output.mem_size := SIZE_HALFWORD;
-					else
-						v_output.mem_size := SIZE_WORD;
-					end if;
-				elsif input.operation = OP_CSRRW or input.operation = OP_CSRRS or input.operation = OP_CSRRC then
-					if input.operation = OP_CSRRW then
-						csr_set_bits := input.operand1;
-						csr_clear_bits := input.operand1;
-					elsif input.operation = OP_CSRRS then
-						csr_set_bits := input.operand1;
-						csr_clear_bits := (others => '1');
-					elsif input.operation = OP_CSRRC then
-						csr_clear_bits := not input.operand1;
-					else
-						assert false report "Unhandled CSR operation in execute stage" severity failure;
-					end if;
-					-- TODO: implementations for CSR read-write registers
-					if input.operand2(11 downto 0) = CSR_MSTATUS then
-						v_output.result := "000000000000000000011000" & mstatus_mpie & "000" & mstatus_mie & "000";
-						mstatus_mie <= (mstatus_mie or csr_set_bits(3)) and csr_clear_bits(3);
-						mstatus_mpie <= (mstatus_mpie or csr_set_bits(7)) and csr_clear_bits(7);
-					elsif input.operand2(11 downto 0) = CSR_MISA then
-						v_output.result := MISA_VALUE;
-					elsif input.operand2(11 downto 0) = CSR_MIE then
-						v_output.result := x"0000" & mie;
-						mie <= (mie or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
-					elsif input.operand2(11 downto 0) = CSR_MTVEC then
-						v_output.result := mtvec_address & "0" & mtvec_mode;
-						mtvec_address <= (mtvec_address or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
-						mtvec_mode <= (mtvec_mode or csr_set_bits(0)) and csr_clear_bits(0);
-					elsif input.operand2(11 downto 0) = CSR_MSTATUSH then
-						v_output.result := (others => '0');
-					elsif input.operand2(11 downto 0) = CSR_MSCRATCH then
-						v_output.result := mscratch;
-						mscratch <= (mscratch or csr_set_bits) and csr_clear_bits;
-					elsif input.operand2(11 downto 0) = CSR_MEPC then
-						v_output.result := mepc & "00";
-						mepc <= (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
-					elsif input.operand2(11 downto 0) = CSR_MCAUSE then
-						v_output.result := mcause_int & "0000000000000000000000000" & mcause_code;
-						mcause_int <= (mcause_int or csr_set_bits(31)) and csr_clear_bits(31);
-						mcause_code <= (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
-					elsif input.operand2(11 downto 0) = CSR_MTVAL then
-						v_output.result := mtval;
-						mtval <= (mtval or csr_set_bits) and csr_clear_bits;
-					elsif input.operand2(11 downto 0) = CSR_MIP then
-						v_output.result := x"0000" & mip;
-						mip <= (mip or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
-					elsif input.operand2(11 downto 0) = CSR_MCYCLE then
-						v_output.result := mcycle;
-						v_mcycle_next := (mcycle or csr_set_bits) and csr_clear_bits;
-					elsif input.operand2(11 downto 0) = CSR_MINSTRET then
-						v_output.result := minstret;
-						v_minstret_next := (minstret or csr_set_bits) and csr_clear_bits;
-					elsif unsigned(CSR_MHPMCOUNTER3) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMCOUNTER31) then
-						v_output.result := (others => '0');
-					elsif input.operand2(11 downto 0) = CSR_MCYCLEH then
-						v_output.result := mcycleh;
-						v_mcycleh_next := (mcycleh or csr_set_bits) and csr_clear_bits;
-					elsif input.operand2(11 downto 0) = CSR_MINSTRETH then
-						v_output.result := minstreth;
-						v_minstreth_next := (minstreth or csr_set_bits) and csr_clear_bits;
-					elsif unsigned(CSR_MHPMCOUNTER3H) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMCOUNTER31H) then
-						v_output.result := (others => '0');
-					elsif unsigned(CSR_MHPMEVENT3) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMEVENT31) then
-						v_output.result := (others => '0');
-					elsif unsigned(CSR_MHPMEVENT3H) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMEVENT31H) then
-						v_output.result := (others => '0');
-					elsif input.csr_read_only = '1' then
-						-- read-only CSRs
-						if input.operand2(11 downto 0) = CSR_MVENDORID then
-							v_output.result := MVENDORID_VALUE;
-						elsif input.operand2(11 downto 0) = CSR_MARCHID then
-							v_output.result := MARCHID_VALUE;
-						elsif input.operand2(11 downto 0) = CSR_MIMPID then
-							v_output.result := MIMPID_VALUE;
-						elsif input.operand2(11 downto 0) = CSR_MHARTID then
-							v_output.result := MHARTID_VALUE;
-						elsif input.operand2(11 downto 0) = CSR_MCONFIGPTR then
-							v_output.result := MCONFIGPTR_VALUE;
 						else
-							-- TODO: exception; trying to read non-existent CSR
 						end if;
 					else
-						-- TODO: exception; trying to write to non-existent or read-only CSR
 					end if;
-				elsif input.operation = OP_MRET then
-					mstatus_mie <= mstatus_mpie;
-					mstatus_mpie <= '1';
-					v_jump := '1';
-					v_jump_address := mepc & "00";
-				elsif input.operation = OP_LED then
-					led <= input.operand1(7 downto 0);
-				else
-					assert false report "Unhandled operation value in execute stage" severity failure;
 				end if;
-				v_output.destination_reg := input.destination_reg;
 			end if;
 			output <= v_output;
 			mem_req <= v_mem_req;
 			jump <= v_jump;
 			jump_address <= v_jump_address(31 downto 1) & "0";
-			mcycle <= v_mcycle_next;
-			mcycleh <= v_mcycleh_next;
-			minstret <= v_minstret_next;
-			minstreth <= v_minstreth_next;
 		end if;
 	end process;

 	signal mscratch: std_logic_vector(31 downto 0) := (others => '0');
 	signal mepc: std_logic_vector(29 downto 0) := (others => '0');
 	signal mcause_int: std_logic := '0';
+	signal mcause_code: std_logic_vector(3 downto 0) := (others => '0');
 	signal mtval: std_logic_vector(31 downto 0) := (others => '0');
 	signal mip: std_logic_vector(15 downto 0) := (others => '0');
 	signal mcycle: std_logic_vector(31 downto 0) := (others => '0');
 		variable v_jump: std_logic;
 		variable v_jump_address: std_logic_vector(31 downto 0);
 		variable v_mem_req: mem_req_t;
+		variable v_mcycle_inc, v_mcycleh_inc: std_logic_vector(31 downto 0);
+		variable v_mcycle, v_mcycleh: std_logic_vector(31 downto 0);
+		variable v_minstret_inc, v_minstreth_inc: std_logic_vector(31 downto 0);
+		variable v_minstret, v_minstreth: std_logic_vector(31 downto 0);
+		variable v_mepc: std_logic_vector(29 downto 0);
+		variable v_mcause_int: std_logic;
+		variable v_mcause_code: std_logic_vector(3 downto 0);
+		variable v_address, v_value: std_logic_vector(31 downto 0);
 		variable csr_set_bits, csr_clear_bits: std_logic_vector(31 downto 0);
 		variable v_temp: unsigned(63 downto 0);
+		variable has_exception: boolean;
+		variable exception_cause: std_logic_vector(3 downto 0);
 	begin
 		if rising_edge(clk) then
 			v_output := DEFAULT_EXECUTE_OUTPUT;
 			v_jump_address := (others => '0');
 			v_temp := unsigned(mcycleh & mcycle) + 1;
+			v_mcycle_inc := std_logic_vector(v_temp(31 downto 0));
+			v_mcycle := v_mcycle_inc;
+			v_mcycleh_inc := std_logic_vector(v_temp(63 downto 32));
+			v_mcycleh := v_mcycleh_inc;
+			v_mepc := mepc;
+			v_mcause_int := mcause_int;
+			v_mcause_code := mcause_code;
+			has_exception := false;
+			exception_cause := (others => '0');
 			v_temp := unsigned(minstreth & minstret);
 			if instr_retire = '1' then
 				v_temp := v_temp + 1;
 			end if;
+			v_minstret := std_logic_vector(v_temp(31 downto 0));
+			v_minstreth := std_logic_vector(v_temp(63 downto 32));
+			if input.is_active = '1' then
+				if input.is_invalid_address = '1' then
+					has_exception := true;
+					exception_cause := EX_CAUSE_INSTRUCTION_ACCESS_FAULT;
+				elsif input.is_invalid = '1' then
+					has_exception := true;
+					exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
+				else
+					if input.operation = OP_ADD then
+						v_output.result := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
+					elsif input.operation = OP_SUB then
+						v_output.result := std_logic_vector(unsigned(input.operand1) - unsigned(input.operand2));
+					elsif input.operation = OP_SLT then
+						if signed(input.operand1) < signed(input.operand2) then
+							v_output.result := std_logic_vector(to_unsigned(1, 32));
+						else
+							v_output.result := (others => '0');
+						end if;
+					elsif input.operation = OP_SLTU then
+						if unsigned(input.operand1) < unsigned(input.operand2) then
+							v_output.result := std_logic_vector(to_unsigned(1, 32));
+						else
+							v_output.result := (others => '0');
+						end if;
+					elsif input.operation = OP_XOR then
+						v_output.result := input.operand1 xor input.operand2;
+					elsif input.operation = OP_OR then
+						v_output.result := input.operand1 or input.operand2;
+					elsif input.operation = OP_AND then
+						v_output.result := input.operand1 and input.operand2;
+					elsif input.operation = OP_SLL then
+						v_output.result := input.operand1;
+						if input.operand2(4) = '1' then
+							v_output.result := v_output.result(15 downto 0) & "0000000000000000";
+						end if;
+						if input.operand2(3) = '1' then
+							v_output.result := v_output.result(23 downto 0) & "00000000";
+						end if;
+						if input.operand2(2) = '1' then
+							v_output.result := v_output.result(27 downto 0) & "0000";
+						end if;
+						if input.operand2(1) = '1' then
+							v_output.result := v_output.result(29 downto 0) & "00";
+						end if;
+						if input.operand2(0) = '1' then
+							v_output.result := v_output.result(30 downto 0) & "0";
+						end if;
+					elsif input.operation = OP_SRL or input.operation = OP_SRA then
+						v_output.result := input.operand1;
+						if input.operation = OP_SRL then
+							v_sign := (others => '0');
+						else
+							v_sign := (others => input.operand1(31));
+						end if;
+						if input.operand2(4) = '1' then
+							v_output.result := v_sign(15 downto 0) & v_output.result(31 downto 16);
+						end if;
+						if input.operand2(3) = '1' then
+							v_output.result := v_sign(7 downto 0) & v_output.result(31 downto 8);
+						end if;
+						if input.operand2(2) = '1' then
+							v_output.result := v_sign(3 downto 0) & v_output.result(31 downto 4);
+						end if;
+						if input.operand2(1) = '1' then
+							v_output.result := v_sign(2 downto 0) & v_output.result(31 downto 3);
+						end if;
+						if input.operand2(0) = '1' then
+							v_output.result := v_sign(1 downto 0) & v_output.result(31 downto 2);
+						end if;
+					elsif input.operation = OP_JAL then
 						v_jump := '1';
+						v_jump_address := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
+						v_output.result := input.operand3;
+					elsif input.operation = OP_BEQ then
+						if input.operand1 = input.operand2 then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_BNE then
+						if input.operand1 /= input.operand2 then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_BLT then
+						if signed(input.operand1) < signed(input.operand2) then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_BGE then
+						if signed(input.operand1) >= signed(input.operand2) then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_BLTU then
+						if unsigned(input.operand1) < unsigned(input.operand2) then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_BGEU then
+						if unsigned(input.operand1) >= unsigned(input.operand2) then
+							v_jump := '1';
+							v_jump_address := input.operand3;
+						end if;
+					elsif input.operation = OP_SB then
+						v_address := input.operand1;
+						v_value := input.operand2;
+						v_mem_req.active := '1';
+						v_mem_req.address := v_address;
+						if v_address(1 downto 0) = "00" then
+							v_mem_req.value := x"000000" & v_value(7 downto 0);
+							v_mem_req.write_enable := "0001";
+						elsif v_address(1 downto 0) = "01" then
+							v_mem_req.value := x"0000" & v_value(7 downto 0) & x"00";
+							v_mem_req.write_enable := "0010";
+						elsif v_address(1 downto 0) = "10" then
+							v_mem_req.value := x"00" & v_value(7 downto 0) & x"0000";
+							v_mem_req.write_enable := "0100";
+						else
+							v_mem_req.value := v_value(7 downto 0) & x"000000";
+							v_mem_req.write_enable := "1000";
+						end if;
+						if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+							has_exception := true;
+							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
+						end if;
+					elsif input.operation = OP_SH then
+						v_address := input.operand1;
+						v_value := input.operand2;
+						v_mem_req.active := '1';
+						v_mem_req.address := v_address;
+						if input.operand1(1 downto 0) = "00" then
+							v_mem_req.value := x"0000" & v_value(15 downto 0);
+							v_mem_req.write_enable := "0011";
+						else
+							v_mem_req.value := v_value(15 downto 0) & x"0000";
+							v_mem_req.write_enable := "1100";
+						end if;
+						if v_address(0) /= '0' then
+							has_exception := true;
+							exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
+						elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+							has_exception := true;
+							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
+						end if;
+					elsif input.operation = OP_SW then
+						v_mem_req.active := '1';
+						v_mem_req.write_enable := "1111";
+						v_mem_req.address := input.operand1;
+						v_mem_req.value := input.operand2;
+						if v_address(1 downto 0) /= "00" then
+							has_exception := true;
+							exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
+						elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+							has_exception := true;
+							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
+						end if;
+					elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or input.operation = OP_LBU or input.operation = OP_LHU then
+						v_address := input.operand1;
+						v_output.use_mem := '1';
+						v_output.mem_addr := v_address(1 downto 0);
+						v_mem_req.active := '1';
+						v_mem_req.address := v_address;
+						if input.operation = OP_LB or input.operation = OP_LH then
+							v_output.mem_sign_extend := '1';
+						end if;
+						if input.operation = OP_LB or input.operation = OP_LBU then
+							v_output.mem_size := SIZE_BYTE;
+							if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+								has_exception := true;
+								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+							end if;
+						elsif input.operation = OP_LH or input.operation = OP_LHU then
+							v_output.mem_size := SIZE_HALFWORD;
+							if v_address(0) /= '0' then
+								has_exception := true;
+								exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
+							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+								has_exception := true;
+								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+							end if;
+						else
+							v_output.mem_size := SIZE_WORD;
+							if v_address(1 downto 0) /= "00" then
+								has_exception := true;
+								exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
+							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+								has_exception := true;
+								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+							end if;
+						end if;
+					elsif input.operation = OP_CSRRW or input.operation = OP_CSRRS or input.operation = OP_CSRRC then
+						if input.operation = OP_CSRRW then
+							csr_set_bits := input.operand1;
+							csr_clear_bits := input.operand1;
+						elsif input.operation = OP_CSRRS then
+							csr_set_bits := input.operand1;
+							csr_clear_bits := (others => '1');
+						elsif input.operation = OP_CSRRC then
+							csr_clear_bits := not input.operand1;
+						else
+							assert false report "Unhandled CSR operation in execute stage" severity failure;
+						end if;
+						-- TODO: implementations for CSR read-write registers
+						if input.operand2(11 downto 0) = CSR_MSTATUS then
+							v_output.result := "000000000000000000011000" & mstatus_mpie & "000" & mstatus_mie & "000";
+							mstatus_mie <= (mstatus_mie or csr_set_bits(3)) and csr_clear_bits(3);
+							mstatus_mpie <= (mstatus_mpie or csr_set_bits(7)) and csr_clear_bits(7);
+						elsif input.operand2(11 downto 0) = CSR_MISA then
+							v_output.result := MISA_VALUE;
+						elsif input.operand2(11 downto 0) = CSR_MIE then
+							v_output.result := x"0000" & mie;
+							mie <= (mie or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
+						elsif input.operand2(11 downto 0) = CSR_MTVEC then
+							v_output.result := mtvec_address & "0" & mtvec_mode;
+							mtvec_address <= (mtvec_address or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
+							mtvec_mode <= (mtvec_mode or csr_set_bits(0)) and csr_clear_bits(0);
+						elsif input.operand2(11 downto 0) = CSR_MSTATUSH then
+							v_output.result := (others => '0');
+						elsif input.operand2(11 downto 0) = CSR_MSCRATCH then
+							v_output.result := mscratch;
+							mscratch <= (mscratch or csr_set_bits) and csr_clear_bits;
+						elsif input.operand2(11 downto 0) = CSR_MEPC then
+							v_output.result := mepc & "00";
+							v_mepc := (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
+						elsif input.operand2(11 downto 0) = CSR_MCAUSE then
+							v_output.result := mcause_int & "000000000000000000000000000" & mcause_code;
+							mcause_int <= (mcause_int or csr_set_bits(31)) and csr_clear_bits(31);
+							mcause_code <= (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
+						elsif input.operand2(11 downto 0) = CSR_MTVAL then
+							v_output.result := mtval;
+							mtval <= (mtval or csr_set_bits) and csr_clear_bits;
+						elsif input.operand2(11 downto 0) = CSR_MIP then
+							v_output.result := x"0000" & mip;
+							mip <= (mip or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
+						elsif input.operand2(11 downto 0) = CSR_MCYCLE then
+							v_output.result := mcycle;
+							v_mcycle := (mcycle or csr_set_bits) and csr_clear_bits;
+						elsif input.operand2(11 downto 0) = CSR_MINSTRET then
+							v_output.result := minstret;
+							v_minstret := (minstret or csr_set_bits) and csr_clear_bits;
+						elsif unsigned(CSR_MHPMCOUNTER3) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMCOUNTER31) then
+							v_output.result := (others => '0');
+						elsif input.operand2(11 downto 0) = CSR_MCYCLEH then
+							v_output.result := mcycleh;
+							v_mcycleh := (mcycleh or csr_set_bits) and csr_clear_bits;
+						elsif input.operand2(11 downto 0) = CSR_MINSTRETH then
+							v_output.result := minstreth;
+							v_minstreth := (minstreth or csr_set_bits) and csr_clear_bits;
+						elsif unsigned(CSR_MHPMCOUNTER3H) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMCOUNTER31H) then
+							v_output.result := (others => '0');
+						elsif unsigned(CSR_MHPMEVENT3) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMEVENT31) then
+							v_output.result := (others => '0');
+						elsif unsigned(CSR_MHPMEVENT3H) <= unsigned(input.operand2(11 downto 0)) and unsigned(input.operand2(11 downto 0)) <= unsigned(CSR_MHPMEVENT31H) then
+							v_output.result := (others => '0');
+						elsif input.csr_read_only = '1' then
+							-- read-only CSRs
+							if input.operand2(11 downto 0) = CSR_MVENDORID then
+								v_output.result := MVENDORID_VALUE;
+							elsif input.operand2(11 downto 0) = CSR_MARCHID then
+								v_output.result := MARCHID_VALUE;
+							elsif input.operand2(11 downto 0) = CSR_MIMPID then
+								v_output.result := MIMPID_VALUE;
+							elsif input.operand2(11 downto 0) = CSR_MHARTID then
+								v_output.result := MHARTID_VALUE;
+							elsif input.operand2(11 downto 0) = CSR_MCONFIGPTR then
+								v_output.result := MCONFIGPTR_VALUE;
+							else
+								-- trying to read non-existent CSR
+								has_exception := true;
+								exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
+							end if;
 						else
+							-- trying to write to non-existent or read-only CSR
+							has_exception := true;
+							exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
 						end if;
+					elsif input.operation = OP_MRET then
+						mstatus_mie <= mstatus_mpie;
+						mstatus_mpie <= '1';
+						v_jump := '1';
+						v_jump_address := mepc & "00";
+						-- TODO: reset mepc?
+					elsif input.operation = OP_ECALL then
+						has_exception := true;
+						exception_cause := EX_CAUSE_ENVIRONMENT_CALL;
+					elsif input.operation = OP_EBREAK then
+						has_exception := true;
+						exception_cause := EX_CAUSE_BREAKPOINT;
+					elsif input.operation = OP_LED then
+						led <= input.operand1(7 downto 0);
 					else
+						assert false report "Unhandled operation value in execute stage" severity failure;
 					end if;
+					v_output.destination_reg := input.destination_reg;
+				end if;
+				if v_jump = '1' and v_jump_address(1) /= '0' then
+					has_exception := true;
+					exception_cause := EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
 				end if;
+				if has_exception then
+					v_output := DEFAULT_EXECUTE_OUTPUT;
+					v_output.is_active := '1';  -- needed to trigger the next instruction
+					v_mem_req := DEFAULT_MEM_REQ;
+					v_jump := '1';
+					v_jump_address := mtvec_address & "00";
+					v_mcycle := v_mcycle_inc;
+					v_mcycleh := v_mcycleh_inc;
+					v_minstret := v_minstret_inc;
+					v_minstreth := v_minstreth_inc;
+					v_mepc := input.pc(31 downto 2);
+					v_mcause_int := '0';
+					v_mcause_code := exception_cause;
+				end if;
 			end if;
 			output <= v_output;
 			mem_req <= v_mem_req;
 			jump <= v_jump;
 			jump_address <= v_jump_address(31 downto 1) & "0";
+			mcycle <= v_mcycle;
+			mcycleh <= v_mcycleh;
+			minstret <= v_minstret;
+			minstreth <= v_minstreth;
+			mepc <= v_mepc;
+			mcause_int <= v_mcause_int;
+			mcause_code <= v_mcause_code;
 		end if;
 	end process;

src/core/types.vhd CHANGED Viewed

@@ -33,6 +33,8 @@ package core_types is
 		OP_CSRRS,
 		OP_CSRRC,
 		OP_MRET,
 		OP_LED
 	);
@@ -45,12 +47,14 @@ package core_types is
 	type decode_output_t is record
 		is_active: std_logic;
 		is_invalid: std_logic;
 		operation: operation_t;
 		operand1: std_logic_vector(31 downto 0);
 		operand2: std_logic_vector(31 downto 0);
 		operand3: std_logic_vector(31 downto 0);
 		destination_reg: std_logic_vector(4 downto 0);
 		csr_read_only: std_logic;
 	end record decode_output_t;
 	type read_size_t is (SIZE_WORD, SIZE_HALFWORD, SIZE_BYTE);

 		OP_CSRRS,
 		OP_CSRRC,
 		OP_MRET,
+		OP_ECALL,
+		OP_EBREAK,
 		OP_LED
 	);
 	type decode_output_t is record
 		is_active: std_logic;
 		is_invalid: std_logic;
+		is_invalid_address: std_logic;
 		operation: operation_t;
 		operand1: std_logic_vector(31 downto 0);
 		operand2: std_logic_vector(31 downto 0);
 		operand3: std_logic_vector(31 downto 0);
 		destination_reg: std_logic_vector(4 downto 0);
 		csr_read_only: std_logic;
+		pc: std_logic_vector(31 downto 0);
 	end record decode_output_t;
 	type read_size_t is (SIZE_WORD, SIZE_HALFWORD, SIZE_BYTE);

...

src/core/constants.vhd CHANGED Viewed

@@ -80,6 +80,9 @@ package core_constants is
 	constant MISA_VALUE: std_logic_vector(31 downto 0) := X"40000100";  -- 32-bit RVI
 	constant EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0000";
 	constant EX_CAUSE_INSTRUCTION_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0001";
 	constant EX_CAUSE_ILLEGAL_INSTRUCTION: std_logic_vector(3 downto 0) := "0010";

 	constant MISA_VALUE: std_logic_vector(31 downto 0) := X"40000100";  -- 32-bit RVI
+	constant MTIME_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFF8";
+	constant MTIMEH_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFFC";
 	constant EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0000";
 	constant EX_CAUSE_INSTRUCTION_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0001";
 	constant EX_CAUSE_ILLEGAL_INSTRUCTION: std_logic_vector(3 downto 0) := "0010";

src/core/execute.vhd CHANGED Viewed

@@ -38,6 +38,8 @@ architecture rtl of execute is
 	signal minstret: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcycleh: std_logic_vector(31 downto 0) := (others => '0');
 	signal minstreth: std_logic_vector(31 downto 0) := (others => '0');
 begin
 	process (clk)
@@ -53,6 +55,8 @@ begin
 		variable v_mepc: std_logic_vector(29 downto 0);
 		variable v_mcause_int: std_logic;
 		variable v_mcause_code: std_logic_vector(3 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
@@ -75,10 +79,17 @@ begin
 			v_mcycle := v_mcycle_inc;
 			v_mcycleh_inc := std_logic_vector(v_temp(63 downto 32));
 			v_mcycleh := v_mcycleh_inc;
 			v_mepc := mepc;
 			v_mcause_int := mcause_int;
 			v_mcause_code := mcause_code;
 			has_exception := false;
 			exception_cause := (others => '0');
@@ -244,54 +255,66 @@ begin
 							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SW then
-						v_mem_req.active := '1';
-						v_mem_req.write_enable := "1111";
 						v_mem_req.address := input.operand1;
-						v_mem_req.value := input.operand2;
-						if v_address(1 downto 0) /= "00" then
-							has_exception := true;
-							exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
-						elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
-							has_exception := true;
-							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
-						end if;
-					elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or input.operation = OP_LBU or input.operation = OP_LHU then
-						v_address := input.operand1;
-						v_output.use_mem := '1';
-						v_output.mem_addr := v_address(1 downto 0);
-						v_mem_req.active := '1';
-						v_mem_req.address := v_address;
-						if input.operation = OP_LB or input.operation = OP_LH then
-							v_output.mem_sign_extend := '1';
-						end if;
-						if input.operation = OP_LB or input.operation = OP_LBU then
-							v_output.mem_size := SIZE_BYTE;
-							if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
-								has_exception := true;
-								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
-							end if;
-						elsif input.operation = OP_LH or input.operation = OP_LHU then
-							v_output.mem_size := SIZE_HALFWORD;
-							if v_address(0) /= '0' then
 								has_exception := true;
-								exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
 							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 								has_exception := true;
-								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
 							end if;
 						else
-							v_output.mem_size := SIZE_WORD;
-							if v_address(1 downto 0) /= "00" then
-								has_exception := true;
-								exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
-							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
-								has_exception := true;
-								exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
 							end if;
 						end if;
 					elsif input.operation = OP_CSRRW or input.operation = OP_CSRRS or input.operation = OP_CSRRC then
@@ -416,6 +439,8 @@ begin
 					v_jump_address := mtvec_address & "00";
 					v_mcycle := v_mcycle_inc;
 					v_mcycleh := v_mcycleh_inc;
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
@@ -430,6 +455,8 @@ begin
 			jump_address <= v_jump_address(31 downto 1) & "0";
 			mcycle <= v_mcycle;
 			mcycleh <= v_mcycleh;
 			minstret <= v_minstret;
 			minstreth <= v_minstreth;
 			mepc <= v_mepc;

 	signal minstret: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcycleh: std_logic_vector(31 downto 0) := (others => '0');
 	signal minstreth: std_logic_vector(31 downto 0) := (others => '0');
+	signal mtime: std_logic_vector(31 downto 0) := (others => '0');
+	signal mtimeh: std_logic_vector(31 downto 0) := (others => '0');
 begin
 	process (clk)
 		variable v_mepc: std_logic_vector(29 downto 0);
 		variable v_mcause_int: std_logic;
 		variable v_mcause_code: std_logic_vector(3 downto 0);
+		variable v_mtime_inc, v_mtimeh_inc: std_logic_vector(31 downto 0);
+		variable v_mtime, v_mtimeh: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
 			v_mcycle := v_mcycle_inc;
 			v_mcycleh_inc := std_logic_vector(v_temp(63 downto 32));
 			v_mcycleh := v_mcycleh_inc;
 			v_mepc := mepc;
 			v_mcause_int := mcause_int;
 			v_mcause_code := mcause_code;
+			v_temp := unsigned(mtimeh & mtime) + 1;
+			v_mtime_inc := std_logic_vector(v_temp(31 downto 0));
+			v_mtime := v_mtime_inc;
+			v_mtimeh_inc := std_logic_vector(v_temp(63 downto 32));
+			v_mtimeh := v_mtimeh_inc;
 			has_exception := false;
 			exception_cause := (others => '0');
 							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SW then
 						v_mem_req.address := input.operand1;
+						if v_address = MTIME_ADDRESS then
+							v_mtime := input.operand2;
+						elsif v_address = MTIMEH_ADDRESS then
+							v_mtimeh := input.operand2;
+						else
+							v_mem_req.active := '1';
+							v_mem_req.write_enable := "1111";
+							v_mem_req.value := input.operand2;
+							if v_address(1 downto 0) /= "00" then
 								has_exception := true;
+								exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
 							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 								has_exception := true;
+								exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 							end if;
+						end if;
+					elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or input.operation = OP_LBU or input.operation = OP_LHU then
+						v_address := input.operand1;
+						if input.operation = OP_LW and v_address = MTIME_ADDRESS then
+							v_output.result := mtime;
+						elsif input.operation = OP_LW and v_address = MTIMEH_ADDRESS then
+							v_output.result := mtimeh;
 						else
+							v_output.use_mem := '1';
+							v_output.mem_addr := v_address(1 downto 0);
+							v_mem_req.active := '1';
+							v_mem_req.address := v_address;
+							if input.operation = OP_LB or input.operation = OP_LH then
+								v_output.mem_sign_extend := '1';
+							end if;
+							if input.operation = OP_LB or input.operation = OP_LBU then
+								v_output.mem_size := SIZE_BYTE;
+								if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+									has_exception := true;
+									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+								end if;
+							elsif input.operation = OP_LH or input.operation = OP_LHU then
+								v_output.mem_size := SIZE_HALFWORD;
+								if v_address(0) /= '0' then
+									has_exception := true;
+									exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
+								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+									has_exception := true;
+									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+								end if;
+							else
+								v_output.mem_size := SIZE_WORD;
+								if v_address(1 downto 0) /= "00" then
+									has_exception := true;
+									exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
+								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
+									has_exception := true;
+									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
+								end if;
 							end if;
 						end if;
 					elsif input.operation = OP_CSRRW or input.operation = OP_CSRRS or input.operation = OP_CSRRC then
 					v_jump_address := mtvec_address & "00";
 					v_mcycle := v_mcycle_inc;
 					v_mcycleh := v_mcycleh_inc;
+					v_mtime := v_mtime_inc;
+					v_mtimeh := v_mtimeh_inc;
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
 			jump_address <= v_jump_address(31 downto 1) & "0";
 			mcycle <= v_mcycle;
 			mcycleh <= v_mcycleh;
+			mtime <= v_mtime;
+			mtimeh <= v_mtimeh;
 			minstret <= v_minstret;
 			minstreth <= v_minstreth;
 			mepc <= v_mepc;

...

src/bram.vhd CHANGED Viewed

@@ -2,538 +2,543 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 entity bram is
 	port(
 		clka: in std_logic;
 		ena: in std_logic;
 		wea: in std_logic_vector(3 downto 0);
-		addra: in std_logic_vector(11 downto 0);
 		dia: in std_logic_vector(31 downto 0);
 		doa: out std_logic_vector(31 downto 0);
 		clkb: in std_logic;
 		enb: in std_logic;
-		addrb: in std_logic_vector(11 downto 0);
 		dob: out std_logic_vector(31 downto 0)
 	);
 end bram;
 architecture rtl of bram is
 	type ram_type is array (0 to 4095) of std_logic_vector(31 downto 0);
 	shared variable RAM: ram_type := (
-X"008000ef", X"0000006f", X"000025b7", X"05800693", X"30858593", X"00b685b3", X"00000513", X"03200793",
-X"06300713", X"00069603", X"00c787b3", X"0207d063", X"06478793", X"fe07cee3", X"0017b613", X"00268693",
-X"00c50533", X"fed590e3", X"00008067", X"fef756e3", X"f9c78793", X"ff9ff06f", X"001c0011", X"ffe70008",
-X"ffd00021", X"002a0002", X"fff60027", X"ffe6001d", X"002c0018", X"ffffffdb", X"0002fffc", X"fffaffd5",
-X"001dffd4", X"ffd0002f", X"ffee000d", X"001e0012", X"0023ffd4", X"00020012", X"0032ffda", X"0012ffe4",
-X"00200015", X"0012fff8", X"0018ffdf", X"fffa002e", X"0027fff7", X"00300007", X"ffe60029", X"0001ffcc",
-X"ffd8ffff", X"0012ffc4", X"ffa9ffee", X"ffaa0049", X"0045ffd3", X"ffe1ffe8", X"fff4ffbb", X"0054ffb1",
-X"00180053", X"ffb50046", X"ffdaffaf", X"001a0018", X"ffd0ffe6", X"fff6ffcc", X"0004ffa6", X"ffa80036",
-X"fffd001f", X"ffbd005b", X"ffc30041", X"003fffe0", X"ffce0053", X"004bffa6", X"ffe9ffe6", X"ffc3ffe6",
-X"ffbfffa7", X"003c00fa", X"ffd1028c", X"00320058", X"ff8fffc3", X"03370024", X"fcaf001a", X"001bffd2",
-X"0029003a", X"ffd00044", X"000fffd6", X"0031ffea", X"0142004e", X"ffe4001c", X"ffdfffa1", X"ffe40038",
-X"003f0025", X"fff8000d", X"0034ffc7", X"ffdcffc0", X"ffe4fff8", X"0031fec7", X"fff3ffa9", X"038f0018",
-X"ff8bffdd", X"ffbf003c", X"fffd0022", X"00360034", X"fe8d0055", X"fff8ffbd", X"ffea029c", X"00330060",
-X"ffc90008", X"001f0045", X"ffcf0053", X"00a5fd22", X"00550023", X"003cffd3", X"0020014c", X"ffe10024",
-X"00e9ffea", X"0050fd42", X"0361ffe9", X"ffa2fffa", X"00120039", X"03bb00e1", X"ffd10022", X"ff9f0037",
-X"0004fff7", X"002b003f", X"0012ffff", X"004b0007", X"ffb4ff20", X"004f000a", X"ffa5fc7e", X"fffdffd1",
-X"0013ffb6", X"ffd30032", X"0036002e", X"001c0024", X"ffe50008", X"00290037", X"021cffd7", X"003a003c",
-X"fffd004c", X"ffd3fcc1", X"ffb3ffb2", X"ffcefffe", X"fdc40018", X"ffa20003", X"ffcbfe03", X"022fffdd",
-X"fedc0015", X"0010000a", X"032cff9e", X"000affd8", X"0010004a", X"005c00ff", X"ffb7029e", X"ffc50038",
-X"fc56ffd7", X"ffacffc2", X"0059fffb", X"01a7ffe9", X"ff5e003e", X"fd46ffc7", X"002fffb0", X"fc7dfe63",
-X"005cffbb", X"ff6f0142", X"0029003b", X"ffd90027", X"ffde0009", X"ffc6ffe4", X"ffc5022f", X"ffedffa7",
-X"005efff3", X"004d0022", X"ffa5fffe", X"ffa2ffaa", X"ffc1ffbd", X"fffb01ae", X"00460005", X"ffbd001e",
-X"ffe20043", X"ff7dffd9", X"0013ffeb", X"ffa00062", X"02620024", X"ffb80036", X"ffcfffa6", X"ffb3000b",
-X"ffe2ffa3", X"004ffffb", X"003b0043", X"003fffe3", X"ffca0042", X"ff9bfdde", X"0004ffe4", X"0060fffa",
-X"0143ffff", X"ffea01b3", X"ffb0ffb6", X"02920036", X"ffd20058", X"ffe90015", X"ffacffa7", X"00030048",
-X"0028003c", X"ffcf0030", X"fffb0001", X"002eff3d", X"02aeffec", X"ffb00058", X"00510032", X"ffbdffe1",
-X"fe72000f", X"fffffef3", X"fc2efd2e", X"ff670035", X"003d0027", X"02050007", X"ffedffe8", X"002d0013",
-X"00460087", X"004303b6", X"fd60fef5", X"03800029", X"ffdfffbf", X"03730023", X"ffe5ffb8", X"ffafffaa",
-X"ffa90051", X"0058000d", X"0034ffd0", X"ffccffd1", X"fd730075", X"ffa8ffdc", X"ffb9000c", X"00400019",
-X"fff902ef", X"0256ffdf", X"0036ff9e", X"02fe001e", X"ffc4000f", X"ffff02b7", X"0027ffc8", X"ff9e0010",
-X"00630065", X"fdccfeeb", X"ffeb0029", X"ffe9ffb1", X"00f60309", X"02330025", X"03100028", X"0038ffb0",
-X"ffe1ffbb", X"00170003", X"ffa1feb5", X"003ffdcd", X"ffacfffb", X"0010ffd0", X"ffc10054", X"ffef004e",
-X"ffe2ffc3", X"012d0003", X"0080001a", X"fff3fc24", X"0057fff2", X"0055000f", X"0030ffc3", X"0041fdb5",
-X"003f0048", X"02ddfd0e", X"0248ffb1", X"0255ffaf", X"ffd8ffa2", X"ffa2ffbe", X"000f005e", X"0018fff1",
-X"03270043", X"00560052", X"0014ffbe", X"005fffd7", X"0046001a", X"fffd01ae", X"ffd10003", X"fc86001f",
-X"fff90201", X"0027003d", X"0376ffb5", X"0056ff9f", X"008c003c", X"0031ffa9", X"0017002e", X"000afffc",
-X"ffc3feec", X"004c0018", X"ffd6ffc5", X"fff8fdee", X"fd480038", X"ffdaffad", X"0039fede", X"0063ffd9",
-X"00370047", X"001cfe83", X"ffe6ffb5", X"004d0016", X"ffa2fffc", X"ffbc0044", X"000bff0a", X"ffcaffbf",
-X"ffc6ffd2", X"ff9e0038", X"ffa2005e", X"001dfe53", X"00850363", X"00110029", X"fff7ffc6", X"fff40398",
-X"ffe40001", X"0301ffb8", X"0012001f", X"00210052", X"fe890206", X"ff9effb2", X"fff0005c", X"001fffd4",
-X"0041ffcd", X"ffef0028", X"fc910034", X"000e0003", X"001c017e", X"00170026", X"0365021b", X"ffe9ffd2",
-X"fffdffa9", X"036e0316", X"ffd70233", X"0032ffbd", X"00370014", X"ffd1002a", X"ffb2ffd4", X"002cfd5d",
-X"ffeafdbe", X"0015fccb", X"0012001c", X"002afd56", X"00080034", X"fc26ffbe", X"ffbdffb0", X"ffda0006",
-X"ffdaffb0", X"ffe0ffab", X"005fffef", X"0019fffd", X"0013ffed", X"00b2ffc8", X"0037ffea", X"fc3afe9d",
-X"fff8032a", X"ffc8fe7c", X"003301e5", X"ffceffe4", X"ffc0ffb1", X"ffccffe0", X"003dfebd", X"fdbdfebe",
-X"01ddffdb", X"002e01fc", X"fda103cc", X"ffabfc69", X"0019fdf7", X"00200031", X"01dd0017", X"005c0047",
-X"fe2cffca", X"fffb003b", X"feee0126", X"00410014", X"000d011f", X"ffb9fca8", X"0047fea8", X"ffc8004d",
-X"014d005a", X"ffb10038", X"011e0004", X"ffb20059", X"003a0014", X"0336fec7", X"0005fffb", X"0052005c",
-X"00290011", X"0032ffda", X"fc8effb9", X"004bffb5", X"ffd5012a", X"0005002d", X"004a0015", X"003affc9",
-X"0279ffdc", X"002b0039", X"fff8000f", X"0178005d", X"0032fcf3", X"ffbc0037", X"ffef0038", X"0034ffb9",
-X"004901b3", X"ffba0045", X"03520061", X"ffce002c", X"003efff8", X"fef00012", X"0055000f", X"00d6fff2",
-X"ffd2002e", X"02efffcd", X"016b0025", X"ffaeffee", X"ffbc0120", X"fffdffa2", X"00520002", X"0020ffeb",
-X"ffdb0052", X"ffdf0025", X"00340051", X"004a0033", X"ffcd004b", X"0034ffd4", X"0223002b", X"00b902f1",
-X"0053004e", X"ffea0036", X"ffb90019", X"ffd1ffe0", X"002e003c", X"ffaf0050", X"037effdd", X"0045000e",
-X"004affca", X"fffaffe8", X"fdcb0005", X"ffa3ffe2", X"001cfff9", X"ffd9ffab", X"003bffc1", X"fea7ffe2",
-X"004bfd5e", X"fc74fe9e", X"000a026e", X"ffd00004", X"fffe0037", X"fffd0063", X"ffe1ffff", X"003cffca",
-X"00540003", X"00e40028", X"ffa1005c", X"ffceff4f", X"003cffb9", X"001bffda", X"002f004b", X"000cff82",
-X"0047011f", X"ffd9005f", X"01b9fff7", X"ff62ffa4", X"00050024", X"00330031", X"fe09036d", X"ffda00f1",
-X"03cf004a", X"ffef0031", X"ffcb0013", X"001a0035", X"ffabffd7", X"01040016", X"ffedfff9", X"ffd0ffba",
-X"0009010e", X"ffa80047", X"0057ffa9", X"000e0002", X"ffbd0054", X"ffdaffdf", X"ffdb004b", X"fff3000d",
-X"ffff002b", X"00070033", X"ffe3003f", X"fdcd000f", X"ffed003a", X"feed0032", X"0047fff6", X"ffad002a",
-X"ffc2ffec", X"ffe60058", X"ffffff9d", X"ffa1005d", X"ffc2ffdc", X"ffc3001d", X"0059002b", X"0041fff6",
-X"0040030d", X"00100054", X"0013004c", X"fd260062", X"0399ffc1", X"fffc0053", X"ffacfff0", X"ffc7004d",
-X"002e005b", X"fdde0059", X"00370011", X"ffe10033", X"ffc1ffa4", X"0010002f", X"00170014", X"0012ffd5",
-X"ffdd0014", X"02960061", X"001a001c", X"ffeefff0", X"00040058", X"fffd001d", X"0084ffcb", X"ffdc0015",
-X"005fffc5", X"ffba000f", X"0023ffb0", X"ffbe0042", X"001b003f", X"0044fe9a", X"01a7ffe9", X"ffe7003e",
-X"ff2c003f", X"0032000c", X"0010ffe5", X"00240017", X"fff3ff9e", X"00340055", X"004efed2", X"ff3a018e",
-X"ffce0060", X"0052ffd2", X"ffb0ff7f", X"0005fff3", X"ffa7ffb7", X"feb1ffc6", X"00580019", X"fff1ff5c",
-X"005f003d", X"00010045", X"0110001e", X"ffb1ff23", X"001c00a5", X"0006002b", X"0052ffa0", X"fdba0052",
-X"00520012", X"ffbafd83", X"fe29ffa3", X"ffd7fd87", X"ff040061", X"003f003b", X"0010ffda", X"003dffd7",
-X"01510050", X"0045005e", X"0024ffc6", X"0053000f", X"003e039c", X"fff2ffd0", X"ffd5ffd8", X"0043002e",
-X"ffecffdf", X"001c0017", X"0009fd1f", X"ffb3004d", X"00220035", X"ffbaffa9", X"00430046", X"03d3ffcf",
-X"ffa2ffa9", X"fd43002d", X"003affee", X"ffd8003b", X"004c0051", X"004d00f3", X"fffb021c", X"000c0365",
-X"00570385", X"fd800028", X"fdf60003", X"ffd1ff7a", X"ffca0036", X"ffed0374", X"000efef7", X"002b008f",
-X"0013fd8b", X"004e0056", X"fff9ffd1", X"0037ffc5", X"fe6e000b", X"0109ffe3", X"ffc2ffa6", X"0063000b",
-X"fcac0065", X"005cffd0", X"ffb70051", X"0001ffd7", X"ffc00037", X"ffe1ffec", X"ff40ff57", X"00600041",
-X"005a0214", X"0021000f", X"001000ec", X"003f005e", X"00130002", X"003303b5", X"00060014", X"002dffb9",
-X"fffe0348", X"029e005c", X"01aaffe6", X"ffc90012", X"fcde003f", X"005b0059", X"003cffbf", X"ffa10001",
-X"fff8ff9f", X"ffed000f", X"004e003a", X"ffa7ffe0", X"ffd0001b", X"ffa50044", X"00cffd5f", X"fc19fffe",
-X"fc1afffe", X"0042ffbe", X"001e0016", X"0053ffdd", X"ff6affa3", X"ffd90005", X"ffa8ffe9", X"0057ffe4",
-X"0044fe29", X"ffadfe2c", X"ffabffef", X"0047ffd9", X"0053fc4d", X"0024ffdf", X"00190059", X"ffc70381",
-X"0043ffd8", X"ffed02dd", X"0051fd0c", X"00350351", X"ffceffa7", X"ff1e0023", X"ffbc026a", X"fc4effae",
-X"fffcfd1a", X"ff9effc6", X"0046000d", X"0055ffaf", X"fff6000f", X"002bffd7", X"00c203c8", X"0242002e",
-X"ffc60016", X"0063fd05", X"fff60035", X"000effeb", X"001a0182", X"ffffffe7", X"ffa7fef2", X"004fffec",
-X"ffab0042", X"ffff00ec", X"ffd30054", X"ffe90044", X"ffca0036", X"003ffff7", X"023effca", X"00be0006",
-X"00baffba", X"ffbd0051", X"0079ff36", X"ffa2030d", X"fd29005e", X"ffb0fee8", X"00610057", X"ffbe0052",
-X"01cd0057", X"ffdbfd07", X"002bfd78", X"003cff88", X"0053005f", X"0030ffd5", X"0019fffa", X"ffb7fff7",
-X"ffb0fd1e", X"ffef0011", X"0002fff0", X"ffc3fff5", X"ffc503b1", X"0048fe6e", X"ffa60207", X"035bffdb",
-X"005cffe6", X"ffc5000d", X"02c9fef2", X"0041ffac", X"ffca0023", X"00510036", X"ff14ff37", X"ffdf0059",
-X"00520012", X"0141fff3", X"ff40fff8", X"004bfff8", X"00380019", X"fffb002c", X"01940370", X"00040011",
-X"ffcdffcf", X"fff6000a", X"00320048", X"ff75fffd", X"03ceffb0", X"02ba003b", X"005a0029", X"ffcbfc85",
-X"0055ffee", X"000dffb1", X"fddefd95", X"03260047", X"ffec0045", X"ffaaffb0", X"00510005", X"0040ffc0",
-X"0058000c", X"0011feb5", X"0021fffd", X"00150117", X"fff9fd6d", X"004bffe7", X"004b02dc", X"000901ed",
-X"0072fd81", X"0052ffac", X"ff790206", X"005affae", X"fd2c01e2", X"ffe10007", X"fff4ffd2", X"0021005c",
-X"00bdffd8", X"fd16004d", X"019c0022", X"03bafff7", X"fffdfc4f", X"002bffd8", X"00500014", X"0006ffaf",
-X"fe500010", X"fffafff7", X"ffa8ffa2", X"ffbbffd5", X"03a2005b", X"fd8f001d", X"0049ff9e", X"0014ffaa",
-X"0009022d", X"0028ffc9", X"ffd6000f", X"003f002a", X"00390044", X"001a003a", X"ffc4ffa3", X"00060005",
-X"ffbcffdd", X"ffa9ffe5", X"ffaf0036", X"ff7e000e", X"028afff1", X"ffea005f", X"ffb1feea", X"0040febf",
-X"00600024", X"0005ffd2", X"003effc5", X"0052002a", X"0131000d", X"ffdaffc2", X"0055000f", X"ff54000f",
-X"fffcff7f", X"ffc2005a", X"ffadffda", X"ffabffe0", X"ffa70059", X"fff303c3", X"00410055", X"ffd5ff9e",
-X"fd090048", X"00030034", X"003bfc31", X"ffb1fff5", X"005aff23", X"0051001d", X"0292ffed", X"001c0047",
-X"ffd3ffda", X"ff3b002d", X"fff60007", X"03790060", X"02cdffab", X"ffb4003b", X"0003031d", X"0018ffe8",
-X"0131ffe8", X"ffd20041", X"ffb3fd91", X"ffe301ad", X"ff7d000d", X"000effae", X"010affab", X"ffaeffcb",
-X"fff90038", X"0215005b", X"ffd30043", X"ffa4ffb5", X"fffb0067", X"0013000e", X"fe67005a", X"ffda03aa",
-X"0048003a", X"00490039", X"ffc90030", X"00220015", X"035cffcc", X"fc74fff8", X"ffacffc0", X"000bffcc",
-X"fff7004d", X"ff9f0015", X"ffda0061", X"fc2b0026", X"0055ffc8", X"ffd6fffa", X"001dff19", X"0059ffa8",
-X"01780001", X"001b0018", X"0056ffe5", X"0040000e", X"00010060", X"001f0027", X"0041fff7", X"ffa1ffa5",
-X"0284fc7b", X"00090038", X"ffef0008", X"00090015", X"005b004f", X"003efedf", X"00150047", X"fd310023",
-X"02550016", X"0056fff5", X"00490058", X"00200020", X"0052ffac", X"00030002", X"fff40009", X"0016ffe0",
-X"ffcbffa6", X"ffef0035", X"002affad", X"ffb8001e", X"fc580026", X"026dfe0a", X"0041ffe7", X"038803a7",
-X"ffa6005a", X"ffd1ffcb", X"0027ffed", X"022dffd7", X"001affc2", X"ffe9013c", X"0027ffe0", X"fff100d7",
-X"0017ffd3", X"ffd10021", X"fff0ffb2", X"fc500014", X"ffed0036", X"ffe70013", X"ffccffe9", X"0035015b",
-X"025b0060", X"ffecff9d", X"005703e7", X"fffeffbe", X"004c0017", X"fffc0003", X"fdcb0045", X"02e90029",
-X"0042fcac", X"01f7fffe", X"fc220063", X"0136005a", X"005efffb", X"0006ffdc", X"003dfda3", X"025fffe6",
-X"0002ffa3", X"fc6d03d9", X"fd45000f", X"0053ffff", X"fed8ffa9", X"00330031", X"fe950045", X"001cfd22",
-X"ffdd0008", X"000cfdd4", X"027bffe3", X"0001ffdc", X"ff9e002e", X"ffe50034", X"0046fd7d", X"001802e3",
-X"fc41fffc", X"001e01d6", X"ffcaffd2", X"004fffd4", X"0043fde9", X"ffd502a4", X"ffa60062", X"002cfff8",
-X"ffa4ffcc", X"ffa5fce1", X"fffefd9e", X"00340002", X"007b002d", X"0042ffec", X"00430043", X"03b2005a",
-X"0027005b", X"00410045", X"003dffcd", X"ffc8002e", X"ffa80058", X"fffbffe1", X"00d4ffb4", X"ffc3fe49",
-X"00010063", X"ffd9ffcf", X"ffcbffca", X"fd680046", X"003d0239", X"0044fff7", X"00130051", X"ffc20062",
-X"0033ffce", X"ffd5fff6", X"ffcd01e5", X"ff0a0052", X"ffabfdd6", X"0035000e", X"ffff002f", X"ffbe0048",
-X"005f0042", X"ffae0057", X"fff7ffbc", X"fe890046", X"002d0025", X"02890033", X"ffe9005a", X"fd84ffe1",
-X"00140050", X"ff31ffa3", X"0020ffe0", X"ffeaffaf", X"ffa80003", X"004fffea", X"ff94001f", X"01540008",
-X"008dffaf", X"001b0049", X"005b0135", X"ff90ffa8", X"0053004f", X"fe2b0133", X"005502cb", X"ffe7003f",
-X"ffb40009", X"0038fceb", X"fef2ffda", X"ffe9fff9", X"ffc4ff9f", X"001fffd5", X"0048ffe1", X"ffd903c7",
-X"ffe90062", X"ffb60039", X"00610062", X"000c02eb", X"ffbc0038", X"ffc3003d", X"0212ffcf", X"ffcf0042",
-X"0024ff9e", X"001f0040", X"03530012", X"004dffb3", X"ffe800d4", X"000bffa8", X"fcb90008", X"ffb2ffee",
-X"0016ffac", X"0038ffea", X"002fffc8", X"0048ffd1", X"ffacffb8", X"ffd2ffba", X"00120015", X"ffc4feeb",
-X"ffe9fffe", X"ffe4001d", X"ffedffb2", X"ffba0016", X"03e40047", X"000e0056", X"004a001a", X"004f0015",
-X"fff3ffc7", X"ffd4ffce", X"000f0040", X"ffe0ff8d", X"ff75ffe5", X"ffc2fc7a", X"0038ffaf", X"004d0004",
-X"ffaf003c", X"005effb7", X"ffdbffa2", X"004500e5", X"ffcbffe7", X"023effad", X"ffe10359", X"fdc3ff81",
-X"005c01fc", X"fd72fd16", X"000cffcd", X"ffdc004b", X"01360300", X"0055001e", X"fcb1ffd2", X"ffc2ffb0",
-X"0137002a", X"03190103", X"0051ffd2", X"02eb0021", X"ffb501a6", X"0006004b", X"0029fffa", X"ffa4fc4b",
-X"0044ff9b", X"001cffb5", X"ffca01d1", X"ff9f0042", X"0032ffc9", X"ffa8026f", X"ffa2fc58", X"fdc6ffdd",
-X"ffc30005", X"003e0043", X"0038ffdc", X"002bffa8", X"ffaf000b", X"ffecffd1", X"0010fe06", X"02d7fff0",
-X"ffdeffc9", X"ffb8fcb8", X"fff9ffed", X"ffa00060", X"0017ffe9", X"ffa20036", X"ffe4ffa2", X"fffbffd0",
-X"000bfff8", X"ffecffa8", X"0012026c", X"0010ffde", X"00600068", X"00360026", X"fff90198", X"ffecffe8",
-X"ffb8005b", X"ffcd0373", X"ff52003f", X"0008ffa7", X"01befff8", X"ffaf0044", X"fe6fffd2", X"fff7ffb3",
-X"ffe6ffaa", X"004dfce8", X"033500a3", X"005bfcb0", X"003cfd7e", X"ffad001d", X"fe060047", X"ffb4ffcb",
-X"ff72005d", X"fffafc49", X"000fffa5", X"ffa1004d", X"fcf80048", X"ffc2ffa0", X"0352ffc9", X"ffc0ffb8",
-X"fffe0003", X"005d0002", X"ffbc0027", X"00080024", X"ffdfffc7", X"fe230052", X"01b5004d", X"ffa2003f",
-X"0002003b", X"ffdeffd8", X"ffe7ffbf", X"00490061", X"ffff001b", X"ffacfff2", X"004b02d4", X"005bffa5",
-X"ffc1016b", X"ffe30129", X"01ffffb1", X"0022016e", X"001b0022", X"0031003c", X"0112fe8e", X"ff840032",
-X"0005fffb", X"0005fffb", X"ffd2005b", X"ffa8ffc7", X"ffe2feae", X"0042fffa", X"001f004d", X"ffc7ffd5",
-X"004f0012", X"ffde0005", X"0226ffbc", X"003300c7", X"ffa101ef", X"ffcd004a", X"001fffe9", X"ff9dffad",
-X"ffcf02d3", X"ffe4ffb9", X"004cff84", X"0060ffb8", X"0244ffee", X"ffdfff9d", X"00410046", X"004affd9",
-X"fe2affa5", X"00410060", X"ffb0ffec", X"ffafffed", X"001dffdc", X"005affa3", X"001d002c", X"001c00d1",
-X"ffff0003", X"ff95ffd3", X"0060ffdf", X"0008000e", X"ffd50109", X"ffe8ffdf", X"00020062", X"fe650219",
-X"ffa3004d", X"feb40122", X"000c0014", X"0374ffac", X"fd3effd9", X"00100008", X"0017ffb1", X"fd28ffe9",
-X"0005ffb8", X"ff9ffffb", X"ffde0033", X"0039ffec", X"0131ffc2", X"0005ffcd", X"fff2fe10", X"028e0028",
-X"0047ffda", X"0012ffa7", X"001100b7", X"0004ffbe", X"ffb5003e", X"003c000f", X"004f0015", X"ffb70020",
-X"0034fff9", X"fff8fec7", X"fcabfffa", X"ffeffff9", X"ffb80048", X"ffcefff2", X"ffa50033", X"0012005b",
-X"ffa3fff4", X"ffdcffc0", X"0024ffe9", X"ffe6fff3", X"fffbffc2", X"fc510125", X"0011ffce", X"005f004f",
-X"0056ffeb", X"0008ff05", X"016affae", X"003c0003", X"0030ffc1", X"000b0001", X"ffccffc4", X"ffadff1b",
-X"ffb1002b", X"fffbffec", X"039fffb5", X"ffaeffe5", X"fff2010a", X"003f001e", X"00abffde", X"ffbcffe0",
-X"0007005d", X"00b1fff4", X"0015ffaa", X"ffbbffe1", X"ffabfec2", X"0046ffb9", X"ffde0048", X"0050ff9f",
-X"0009ff8b", X"0063005b", X"ffc0ff9d", X"ffcd004a", X"004fffc4", X"0332ffd6", X"0266ffca", X"ffedfd49",
-X"ffddfc2d", X"ffcdfe1a", X"ffe40051", X"0013ffa4", X"000dffe3", X"000cffae", X"ffa10063", X"01250035",
-X"0026ffa1", X"fed2ffcb", X"000a0013", X"002fffc7", X"004a0019", X"ffbf0035", X"ffd7000d", X"ffbdffbc",
-X"ffe7ffba", X"ffa6ffce", X"02fbffa7", X"ffd0035f", X"0052ffbd", X"ff9effc6", X"ffa1fde7", X"002d0025",
-X"ffe602cc", X"fee9ff9e", X"ffc5ffbe", X"ffe8ffb5", X"001e01a8", X"ffd3000f", X"ffb3ffba", X"0019fe9f",
-X"ffc80023", X"ffcf0060", X"0015fd11", X"ffd5002f", X"ffc6ffbd", X"001f0048", X"0036ffaa", X"0364001d",
-X"0019ffbc", X"002a005a", X"00590036", X"ffb7ffe5", X"019c0021", X"ffa9003e", X"0016ffd1", X"ffbeffcb",
-X"ffb70060", X"ff9d0001", X"03100014", X"000d031b", X"fd3cfd9b", X"0045ffc3", X"00530011", X"fddeffca",
-X"0321031f", X"ffe1ffac", X"ffeaffb2", X"ffd50059", X"003b004a", X"fc71ffc0", X"000b0035", X"000b015b",
-X"0044000e", X"ffe10007", X"fe0bffbb", X"0063ff9e", X"fe7cffab", X"00080028", X"00050185", X"03670041",
-X"ffc3fce2", X"001a0036", X"002fffe6", X"005fffdf", X"0324ffad", X"03b4001a", X"0005fff7", X"fff4004b",
-X"ffd3ffee", X"0009ffee", X"010a0009", X"00370022", X"ffa20053", X"ff470029", X"ffb6ffd1", X"005bffb1",
-X"ffacfff9", X"fc3cffdc", X"fdde002e", X"0009fff7", X"00280059", X"ffcbffff", X"0046fe25", X"ffc2fff8",
-X"003c0028", X"005b003c", X"ffcb0031", X"00130022", X"0038fff6", X"ffdeffce", X"ffa4021a", X"000cfc74",
-X"ffa6fff4", X"00030058", X"00380002", X"0006ffbf", X"013dffbf", X"fff9ff68", X"ffc40007", X"00190038",
-X"002ffc20", X"0030fff3", X"fd70ffcc", X"fd0f000f", X"02bd0039", X"ffd30052", X"001301d3", X"ffe80036",
-X"ffdb0020", X"001ffffe", X"005b003d", X"003afdf7", X"0059ff0e", X"ffd2005a", X"004d0398", X"0005ffb3",
-X"ffa90052", X"fff0fe6c", X"ffd0ffd4", X"01a00070", X"fff9ff28", X"020afffa", X"ffe7005b", X"ffdafe4b",
-X"ffb6fc84", X"ffe1fd86", X"ffc10024", X"00280012", X"01f8fffc", X"ffd80028", X"03090003", X"004bfe39",
-X"fffc0057", X"003affad", X"ffbbfd15", X"0013003a", X"fff60051", X"ffbeffa6", X"fffeffce", X"0007ffae",
-X"fe92fff9", X"ffdb0362", X"ffa6001b", X"ff360002", X"038a004f", X"001ffff0", X"0040ffcc", X"0024ffac",
-X"ffd802c6", X"0016ffed", X"0039fd9d", X"0040ffcb", X"fff8000e", X"004c0006", X"0021024d", X"02ec0030",
-X"0060fff5", X"000cffab", X"ffa2ffd2", X"00370046", X"00430111", X"00570371", X"fffffffc", X"ffa6ff9f",
-X"00040057", X"ffc20060", X"ffb2003e", X"0001001c", X"00d8ffbd", X"0013ffed", X"004b0027", X"0061fd36",
-X"ff9d0003", X"fff8ffa0", X"002ffe0d", X"0029ffc7", X"0021ffb7", X"0001000e", X"003fffd3", X"ffd1ffaa",
-X"005b0014", X"00660062", X"ffea0057", X"00560024", X"ff2d0018", X"002cff27", X"002a001e", X"00c7ff9e",
-X"0022ffde", X"005a0032", X"ffe0001c", X"ffc70040", X"0069001b", X"ffea002f", X"012dffdd", X"ffefffcf",
-X"fcf6ffea", X"0006fda2", X"02c4ffe7", X"ffb10024", X"ffe10004", X"ffa4fff3", X"00160188", X"003f004e",
-X"fffe0051", X"00310008", X"ffdbfcd8", X"fe050043", X"ffec0056", X"fefcffb5", X"ffb1001a", X"002fffd9",
-X"0326ffbf", X"ffc70021", X"001fffef", X"fff10060", X"00380036", X"03e50260", X"001f002a", X"0045001f",
-X"fdfcffac", X"000bffaf", X"0003ffdf", X"fd7e0322", X"ffb60028", X"ffa5ffcf", X"0059fc8a", X"ffee000b",
-X"ffe6ffae", X"ffd8ff04", X"ffb1ff9e", X"fcb3ffc4", X"0001ffff", X"0018ffe7", X"ffc90327", X"ffbe000b",
-X"0048ffb7", X"02010005", X"01e5ffbc", X"ffaf0046", X"ffaaffed", X"002effb8", X"ffc5ffa8", X"0175ffd7",
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-X"004d0168", X"ffbcfc7d", X"fe880042", X"004effb2", X"ff9f0061", X"ffb7ffc6", X"ffc90056", X"ffa5fff7",
-X"0005004e", X"000fffda", X"0001027f", X"00420033", X"003bffac", X"feb20008", X"0048ffc9", X"ffa3ffae",
-X"014a005c", X"0040ffa2", X"0057fe19", X"fdca0041", X"0018fd62", X"002a000a", X"0026005f", X"fffc016e",
-X"ffe3001d", X"ffa2005b", X"fd6c0030", X"0056ffd8", X"03880301", X"ffb4fffc", X"ffd3004e", X"fff2ffb7",
-X"ffc6ffba", X"fc97ffbb", X"ffdaff16", X"002effa6", X"ffa3ff9e", X"ffee0025", X"ffd40058", X"0061fdd7",
-X"ffc7fe2b", X"ffd6ffc6", X"01720025", X"012bfeb5", X"ffabffcf", X"00b40055", X"012e0396", X"ffb8ff80",
-X"ffe6fff5", X"ffe7ffc1", X"00050019", X"fff2ffd1", X"00450038", X"fc1e020d", X"fd870215", X"ffcbffff",
-X"fff6ffd2", X"ffcb0062", X"fff3004e", X"ffbe0042", X"ffcf0031", X"ffbefff7", X"03590012", X"ffb80048",
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-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
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-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
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-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
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-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
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-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
-X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000"
 	);
 begin
 	-- port A
@@ -560,4 +565,4 @@ begin
 			end if;
 		end if;
 	end process;
-end rtl;

 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
+use work.types.all;
+use work.constants.all;
 entity bram is
 	port(
 		clka: in std_logic;
 		ena: in std_logic;
 		wea: in std_logic_vector(3 downto 0);
+		addra: in std_logic_vector(MEM_ADDRESS_BITS - 3 downto 0);
 		dia: in std_logic_vector(31 downto 0);
 		doa: out std_logic_vector(31 downto 0);
 		clkb: in std_logic;
 		enb: in std_logic;
+		addrb: in std_logic_vector(MEM_ADDRESS_BITS - 3 downto 0);
 		dob: out std_logic_vector(31 downto 0)
 	);
 end bram;
 architecture rtl of bram is
+-- START PROGMEM
 	type ram_type is array (0 to 4095) of std_logic_vector(31 downto 0);
 	shared variable RAM: ram_type := (
+		X"93020000", X"73930234", X"93028000", X"f3a30234", X"93028000", X"73be0234", X"73600434", X"73700434",
+		X"f32e0034", X"736f0034", X"b7220000", X"93820280", X"f39f0234", X"6f000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
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+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000",
+		X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000", X"00000000"
 	);
+-- END PROGMEM
 begin
 	-- port A
 			end if;
 		end if;
 	end process;
+end rtl;

...

src/core/constants.vhd CHANGED Viewed

@@ -82,6 +82,8 @@ package core_constants is
 	constant MTIME_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFF8";
 	constant MTIMEH_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFFC";
 	constant EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0000";
 	constant EX_CAUSE_INSTRUCTION_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0001";

 	constant MTIME_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFF8";
 	constant MTIMEH_ADDRESS: std_logic_vector(31 downto 0) := X"0200BFFC";
+	constant MTIMECMP_ADDRESS: std_logic_vector(31 downto 0) := X"02004000";
+	constant MTIMECMPH_ADDRESS: std_logic_vector(31 downto 0) := X"02004004";
 	constant EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0000";
 	constant EX_CAUSE_INSTRUCTION_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0001";

src/core/execute.vhd CHANGED Viewed

@@ -40,6 +40,8 @@ architecture rtl of execute is
 	signal minstreth: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtime: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimeh: std_logic_vector(31 downto 0) := (others => '0');
 begin
 	process (clk)
@@ -57,6 +59,7 @@ begin
 		variable v_mcause_code: std_logic_vector(3 downto 0);
 		variable v_mtime_inc, v_mtimeh_inc: std_logic_vector(31 downto 0);
 		variable v_mtime, v_mtimeh: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
@@ -89,6 +92,8 @@ begin
 			v_mtime := v_mtime_inc;
 			v_mtimeh_inc := std_logic_vector(v_temp(63 downto 32));
 			v_mtimeh := v_mtimeh_inc;
 			has_exception := false;
 			exception_cause := (others => '0');
@@ -261,6 +266,10 @@ begin
 							v_mtime := input.operand2;
 						elsif v_address = MTIMEH_ADDRESS then
 							v_mtimeh := input.operand2;
 						else
 							v_mem_req.active := '1';
 							v_mem_req.write_enable := "1111";
@@ -281,6 +290,10 @@ begin
 							v_output.result := mtime;
 						elsif input.operation = OP_LW and v_address = MTIMEH_ADDRESS then
 							v_output.result := mtimeh;
 						else
 							v_output.use_mem := '1';
 							v_output.mem_addr := v_address(1 downto 0);
@@ -441,6 +454,8 @@ begin
 					v_mcycleh := v_mcycleh_inc;
 					v_mtime := v_mtime_inc;
 					v_mtimeh := v_mtimeh_inc;
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
@@ -457,6 +472,8 @@ begin
 			mcycleh <= v_mcycleh;
 			mtime <= v_mtime;
 			mtimeh <= v_mtimeh;
 			minstret <= v_minstret;
 			minstreth <= v_minstreth;
 			mepc <= v_mepc;

 	signal minstreth: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtime: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimeh: std_logic_vector(31 downto 0) := (others => '0');
+	signal mtimecmp: std_logic_vector(31 downto 0) := (others => '0');
+	signal mtimecmph: std_logic_vector(31 downto 0) := (others => '0');
 begin
 	process (clk)
 		variable v_mcause_code: std_logic_vector(3 downto 0);
 		variable v_mtime_inc, v_mtimeh_inc: std_logic_vector(31 downto 0);
 		variable v_mtime, v_mtimeh: std_logic_vector(31 downto 0);
+		variable v_mtimecmp, v_mtimecmph: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
 			v_mtime := v_mtime_inc;
 			v_mtimeh_inc := std_logic_vector(v_temp(63 downto 32));
 			v_mtimeh := v_mtimeh_inc;
+			v_mtimecmp := mtimecmp;
+			v_mtimecmph := mtimecmph;
 			has_exception := false;
 			exception_cause := (others => '0');
 							v_mtime := input.operand2;
 						elsif v_address = MTIMEH_ADDRESS then
 							v_mtimeh := input.operand2;
+						elsif v_address = MTIMECMP_ADDRESS then
+							v_mtimecmp := input.operand2;
+						elsif v_address = MTIMECMPH_ADDRESS then
+							v_mtimecmph := input.operand2;
 						else
 							v_mem_req.active := '1';
 							v_mem_req.write_enable := "1111";
 							v_output.result := mtime;
 						elsif input.operation = OP_LW and v_address = MTIMEH_ADDRESS then
 							v_output.result := mtimeh;
+						elsif input.operation = OP_LW and v_address = MTIMECMP_ADDRESS then
+							v_output.result := mtimecmp;
+						elsif input.operation = OP_LW and v_address = MTIMECMPH_ADDRESS then
+							v_output.result := mtimecmph;
 						else
 							v_output.use_mem := '1';
 							v_output.mem_addr := v_address(1 downto 0);
 					v_mcycleh := v_mcycleh_inc;
 					v_mtime := v_mtime_inc;
 					v_mtimeh := v_mtimeh_inc;
+					v_mtimecmp := mtimecmp;
+					v_mtimecmph := mtimecmph;
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
 			mcycleh <= v_mcycleh;
 			mtime <= v_mtime;
 			mtimeh <= v_mtimeh;
+			mtimecmp <= v_mtimecmp;
+			mtimecmph <= v_mtimecmph;
 			minstret <= v_minstret;
 			minstreth <= v_minstreth;
 			mepc <= v_mepc;

...

toolchain/program CHANGED Viewed

@@ -28,7 +28,7 @@ with open(BINARY_FILE_PATH, 'rb') as f:
 		if len(word) < 4:
 			raise ValueError(f"Incomplete 32-bit word at offset {i}")
-		buffer[j] = int.from_bytes(word)
 		i += 4
 		j += 1

 		if len(word) < 4:
 			raise ValueError(f"Incomplete 32-bit word at offset {i}")
+		buffer[j] = int.from_bytes(word, byteorder='little')
 		i += 4
 		j += 1

...

src/core/constants.vhd CHANGED Viewed

@@ -94,4 +94,6 @@ package core_constants is
 	constant EX_CAUSE_STORE_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0110";
 	constant EX_CAUSE_STORE_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0111";
 	constant EX_CAUSE_ENVIRONMENT_CALL: std_logic_vector(3 downto 0) := "1011";
 end package core_constants;

 	constant EX_CAUSE_STORE_ADDRESS_MISALIGNED: std_logic_vector(3 downto 0) := "0110";
 	constant EX_CAUSE_STORE_ACCESS_FAULT: std_logic_vector(3 downto 0) := "0111";
 	constant EX_CAUSE_ENVIRONMENT_CALL: std_logic_vector(3 downto 0) := "1011";
+	constant INT_CAUSE_MACHINE_TIMER_INTERRUPT: std_logic_vector(3 downto 0) := "0111";
 end package core_constants;

src/core/execute.vhd CHANGED Viewed

@@ -25,7 +25,7 @@ end execute;
 architecture rtl of execute is
 	signal mstatus_mpie, mstatus_mie: std_logic := '0';
-	signal mie: std_logic_vector(15 downto 0) := (others => '0');
 	signal mtvec_address: std_logic_vector(29 downto 0) := (others => '0');
 	signal mtvec_mode: std_logic := '0';
 	signal mscratch: std_logic_vector(31 downto 0) := (others => '0');
@@ -33,7 +33,6 @@ architecture rtl of execute is
 	signal mcause_int: std_logic := '0';
 	signal mcause_code: std_logic_vector(3 downto 0) := (others => '0');
 	signal mtval: std_logic_vector(31 downto 0) := (others => '0');
-	signal mip: std_logic_vector(15 downto 0) := (others => '0');
 	signal mcycle: std_logic_vector(31 downto 0) := (others => '0');
 	signal minstret: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcycleh: std_logic_vector(31 downto 0) := (others => '0');
@@ -50,6 +49,7 @@ begin
 		variable v_jump: std_logic;
 		variable v_jump_address: std_logic_vector(31 downto 0);
 		variable v_mem_req: mem_req_t;
 		variable v_mcycle_inc, v_mcycleh_inc: std_logic_vector(31 downto 0);
 		variable v_mcycle, v_mcycleh: std_logic_vector(31 downto 0);
 		variable v_minstret_inc, v_minstreth_inc: std_logic_vector(31 downto 0);
@@ -60,6 +60,12 @@ begin
 		variable v_mtime_inc, v_mtimeh_inc: std_logic_vector(31 downto 0);
 		variable v_mtime, v_mtimeh: std_logic_vector(31 downto 0);
 		variable v_mtimecmp, v_mtimecmph: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
@@ -67,7 +73,6 @@ begin
 		variable v_temp: unsigned(63 downto 0);
 		variable has_exception: boolean;
-		variable exception_cause: std_logic_vector(3 downto 0);
 	begin
 		if rising_edge(clk) then
@@ -77,6 +82,9 @@ begin
 			v_jump := '0';
 			v_jump_address := (others => '0');
 			v_temp := unsigned(mcycleh & mcycle) + 1;
 			v_mcycle_inc := std_logic_vector(v_temp(31 downto 0));
 			v_mcycle := v_mcycle_inc;
@@ -94,25 +102,37 @@ begin
 			v_mtimeh := v_mtimeh_inc;
 			v_mtimecmp := mtimecmp;
 			v_mtimecmph := mtimecmph;
 			has_exception := false;
-			exception_cause := (others => '0');
 			v_temp := unsigned(minstreth & minstret);
 			if instr_retire = '1' then
 				v_temp := v_temp + 1;
 			end if;
-			v_minstret := std_logic_vector(v_temp(31 downto 0));
-			v_minstreth := std_logic_vector(v_temp(63 downto 32));
 			if input.is_active = '1' then
 				if input.is_invalid_address = '1' then
 					has_exception := true;
-					exception_cause := EX_CAUSE_INSTRUCTION_ACCESS_FAULT;
 				elsif input.is_invalid = '1' then
 					has_exception := true;
-					exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
 				else
 					if input.operation = OP_ADD then
 						v_output.result := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
@@ -235,7 +255,7 @@ begin
 						if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 							has_exception := true;
-							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SH then
 						v_address := input.operand1;
@@ -254,13 +274,13 @@ begin
 						if v_address(0) /= '0' then
 							has_exception := true;
-							exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
 						elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 							has_exception := true;
-							exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SW then
-						v_mem_req.address := input.operand1;
 						if v_address = MTIME_ADDRESS then
 							v_mtime := input.operand2;
@@ -272,15 +292,16 @@ begin
 							v_mtimecmph := input.operand2;
 						else
 							v_mem_req.active := '1';
 							v_mem_req.write_enable := "1111";
 							v_mem_req.value := input.operand2;
 							if v_address(1 downto 0) /= "00" then
 								has_exception := true;
-								exception_cause := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
 							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 								has_exception := true;
-								exception_cause := EX_CAUSE_STORE_ACCESS_FAULT;
 							end if;
 						end if;
 					elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or input.operation = OP_LBU or input.operation = OP_LHU then
@@ -308,25 +329,25 @@ begin
 								v_output.mem_size := SIZE_BYTE;
 								if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
-									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							elsif input.operation = OP_LH or input.operation = OP_LHU then
 								v_output.mem_size := SIZE_HALFWORD;
 								if v_address(0) /= '0' then
 									has_exception := true;
-									exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
 								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
-									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							else
 								v_output.mem_size := SIZE_WORD;
 								if v_address(1 downto 0) /= "00" then
 									has_exception := true;
-									exception_cause := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
 								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
-									exception_cause := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							end if;
 						end if;
@@ -347,22 +368,22 @@ begin
 						if input.operand2(11 downto 0) = CSR_MSTATUS then
 							v_output.result := "000000000000000000011000" & mstatus_mpie & "000" & mstatus_mie & "000";
-							mstatus_mie <= (mstatus_mie or csr_set_bits(3)) and csr_clear_bits(3);
-							mstatus_mpie <= (mstatus_mpie or csr_set_bits(7)) and csr_clear_bits(7);
 						elsif input.operand2(11 downto 0) = CSR_MISA then
 							v_output.result := MISA_VALUE;
 						elsif input.operand2(11 downto 0) = CSR_MIE then
-							v_output.result := x"0000" & mie;
-							mie <= (mie or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MTVEC then
 							v_output.result := mtvec_address & "0" & mtvec_mode;
-							mtvec_address <= (mtvec_address or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
-							mtvec_mode <= (mtvec_mode or csr_set_bits(0)) and csr_clear_bits(0);
 						elsif input.operand2(11 downto 0) = CSR_MSTATUSH then
 							v_output.result := (others => '0');
 						elsif input.operand2(11 downto 0) = CSR_MSCRATCH then
 							v_output.result := mscratch;
-							mscratch <= (mscratch or csr_set_bits) and csr_clear_bits;
 						elsif input.operand2(11 downto 0) = CSR_MEPC then
 							v_output.result := mepc & "00";
 							v_mepc := (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
@@ -372,10 +393,9 @@ begin
 							mcause_code <= (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MTVAL then
 							v_output.result := mtval;
-							mtval <= (mtval or csr_set_bits) and csr_clear_bits;
 						elsif input.operand2(11 downto 0) = CSR_MIP then
-							v_output.result := x"0000" & mip;
-							mip <= (mip or csr_set_bits(15 downto 0)) and csr_clear_bits(15 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MCYCLE then
 							v_output.result := mcycle;
 							v_mcycle := (mcycle or csr_set_bits) and csr_clear_bits;
@@ -411,25 +431,25 @@ begin
 							else
 								-- trying to read non-existent CSR
 								has_exception := true;
-								exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
 							end if;
 						else
 							-- trying to write to non-existent or read-only CSR
 							has_exception := true;
-							exception_cause := EX_CAUSE_ILLEGAL_INSTRUCTION;
 						end if;
 					elsif input.operation = OP_MRET then
-						mstatus_mie <= mstatus_mpie;
-						mstatus_mpie <= '1';
 						v_jump := '1';
 						v_jump_address := mepc & "00";
 						-- TODO: reset mepc?
 					elsif input.operation = OP_ECALL then
 						has_exception := true;
-						exception_cause := EX_CAUSE_ENVIRONMENT_CALL;
 					elsif input.operation = OP_EBREAK then
 						has_exception := true;
-						exception_cause := EX_CAUSE_BREAKPOINT;
 					elsif input.operation = OP_LED then
 						led <= input.operand1(7 downto 0);
 					else
@@ -439,9 +459,13 @@ begin
 					v_output.destination_reg := input.destination_reg;
 				end if;
-				if v_jump = '1' and v_jump_address(1) /= '0' then
 					has_exception := true;
-					exception_cause := EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
 				end if;
 				if has_exception then
@@ -459,8 +483,15 @@ begin
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
-					v_mcause_int := '0';
-					v_mcause_code := exception_cause;
 				end if;
 			end if;
@@ -479,6 +510,15 @@ begin
 			mepc <= v_mepc;
 			mcause_int <= v_mcause_int;
 			mcause_code <= v_mcause_code;
 		end if;
 	end process;

 architecture rtl of execute is
 	signal mstatus_mpie, mstatus_mie: std_logic := '0';
+	signal mtie: std_logic := '0';
 	signal mtvec_address: std_logic_vector(29 downto 0) := (others => '0');
 	signal mtvec_mode: std_logic := '0';
 	signal mscratch: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcause_int: std_logic := '0';
 	signal mcause_code: std_logic_vector(3 downto 0) := (others => '0');
 	signal mtval: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcycle: std_logic_vector(31 downto 0) := (others => '0');
 	signal minstret: std_logic_vector(31 downto 0) := (others => '0');
 	signal mcycleh: std_logic_vector(31 downto 0) := (others => '0');
 		variable v_jump: std_logic;
 		variable v_jump_address: std_logic_vector(31 downto 0);
 		variable v_mem_req: mem_req_t;
+		variable v_mstatus_mpie, v_mstatus_mie: std_logic;
 		variable v_mcycle_inc, v_mcycleh_inc: std_logic_vector(31 downto 0);
 		variable v_mcycle, v_mcycleh: std_logic_vector(31 downto 0);
 		variable v_minstret_inc, v_minstreth_inc: std_logic_vector(31 downto 0);
 		variable v_mtime_inc, v_mtimeh_inc: std_logic_vector(31 downto 0);
 		variable v_mtime, v_mtimeh: std_logic_vector(31 downto 0);
 		variable v_mtimecmp, v_mtimecmph: std_logic_vector(31 downto 0);
+		variable v_mtip: std_logic;
+		variable v_mtval: std_logic_vector(31 downto 0);
+		variable v_mtie: std_logic;
+		variable v_mtvec_address: std_logic_vector(29 downto 0);
+		variable v_mtvec_mode: std_logic;
+		variable v_mscratch: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
 		variable v_temp: unsigned(63 downto 0);
 		variable has_exception: boolean;
 	begin
 		if rising_edge(clk) then
 			v_jump := '0';
 			v_jump_address := (others => '0');
+			v_mstatus_mie := mstatus_mie;
+			v_mstatus_mpie := mstatus_mpie;
 			v_temp := unsigned(mcycleh & mcycle) + 1;
 			v_mcycle_inc := std_logic_vector(v_temp(31 downto 0));
 			v_mcycle := v_mcycle_inc;
 			v_mtimeh := v_mtimeh_inc;
 			v_mtimecmp := mtimecmp;
 			v_mtimecmph := mtimecmph;
+			v_mtval := mtval;
+			v_mtie := mtie;
+			v_mtvec_address := mtvec_address;
+			v_mtvec_mode := mtvec_mode;
+			v_mscratch := mscratch;
 			has_exception := false;
 			v_temp := unsigned(minstreth & minstret);
 			if instr_retire = '1' then
 				v_temp := v_temp + 1;
 			end if;
+			v_minstret_inc := std_logic_vector(v_temp(31 downto 0));
+			v_minstreth_inc := std_logic_vector(v_temp(63 downto 32));
+			v_minstret := v_minstret_inc;
+			v_minstreth := v_minstret_inc;
+			if unsigned(mtimeh & mtime) > unsigned(mtimecmph & mtimecmp) then
+				v_mtip := '1';
+			else
+				v_mtip := '0';
+			end if;
 			if input.is_active = '1' then
 				if input.is_invalid_address = '1' then
 					has_exception := true;
+					v_mcause_code := EX_CAUSE_INSTRUCTION_ACCESS_FAULT;
 				elsif input.is_invalid = '1' then
 					has_exception := true;
+					v_mcause_code := EX_CAUSE_ILLEGAL_INSTRUCTION;
 				else
 					if input.operation = OP_ADD then
 						v_output.result := std_logic_vector(unsigned(input.operand1) + unsigned(input.operand2));
 						if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 							has_exception := true;
+							v_mcause_code := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SH then
 						v_address := input.operand1;
 						if v_address(0) /= '0' then
 							has_exception := true;
+							v_mcause_code := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
 						elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 							has_exception := true;
+							v_mcause_code := EX_CAUSE_STORE_ACCESS_FAULT;
 						end if;
 					elsif input.operation = OP_SW then
+						v_address := input.operand1;
 						if v_address = MTIME_ADDRESS then
 							v_mtime := input.operand2;
 							v_mtimecmph := input.operand2;
 						else
 							v_mem_req.active := '1';
+							v_mem_req.address := v_address;
 							v_mem_req.write_enable := "1111";
 							v_mem_req.value := input.operand2;
 							if v_address(1 downto 0) /= "00" then
 								has_exception := true;
+								v_mcause_code := EX_CAUSE_STORE_ADDRESS_MISALIGNED;
 							elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 								has_exception := true;
+								v_mcause_code := EX_CAUSE_STORE_ACCESS_FAULT;
 							end if;
 						end if;
 					elsif input.operation = OP_LB or input.operation = OP_LH or input.operation = OP_LW or input.operation = OP_LBU or input.operation = OP_LHU then
 								v_output.mem_size := SIZE_BYTE;
 								if not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
+									v_mcause_code := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							elsif input.operation = OP_LH or input.operation = OP_LHU then
 								v_output.mem_size := SIZE_HALFWORD;
 								if v_address(0) /= '0' then
 									has_exception := true;
+									v_mcause_code := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
 								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
+									v_mcause_code := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							else
 								v_output.mem_size := SIZE_WORD;
 								if v_address(1 downto 0) /= "00" then
 									has_exception := true;
+									v_mcause_code := EX_CAUSE_LOAD_ADDRESS_MISALIGNED;
 								elsif not (MEM_ADDRESS_MIN <= v_address and v_address <= MEM_ADDRESS_MAX) then
 									has_exception := true;
+									v_mcause_code := EX_CAUSE_LOAD_ACCESS_FAULT;
 								end if;
 							end if;
 						end if;
 						if input.operand2(11 downto 0) = CSR_MSTATUS then
 							v_output.result := "000000000000000000011000" & mstatus_mpie & "000" & mstatus_mie & "000";
+							v_mstatus_mie := (mstatus_mie or csr_set_bits(3)) and csr_clear_bits(3);
+							v_mstatus_mpie := (mstatus_mpie or csr_set_bits(7)) and csr_clear_bits(7);
 						elsif input.operand2(11 downto 0) = CSR_MISA then
 							v_output.result := MISA_VALUE;
 						elsif input.operand2(11 downto 0) = CSR_MIE then
+							v_output.result := "000000000000000000000000" & mtie & "0000000";
+							v_mtie := (mtie or csr_set_bits(7)) and csr_clear_bits(7);
 						elsif input.operand2(11 downto 0) = CSR_MTVEC then
 							v_output.result := mtvec_address & "0" & mtvec_mode;
+							v_mtvec_address := (mtvec_address or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
+							v_mtvec_mode := (mtvec_mode or csr_set_bits(0)) and csr_clear_bits(0);
 						elsif input.operand2(11 downto 0) = CSR_MSTATUSH then
 							v_output.result := (others => '0');
 						elsif input.operand2(11 downto 0) = CSR_MSCRATCH then
 							v_output.result := mscratch;
+							v_mscratch := (mscratch or csr_set_bits) and csr_clear_bits;
 						elsif input.operand2(11 downto 0) = CSR_MEPC then
 							v_output.result := mepc & "00";
 							v_mepc := (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
 							mcause_code <= (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MTVAL then
 							v_output.result := mtval;
+							v_mtval := (mtval or csr_set_bits) and csr_clear_bits;
 						elsif input.operand2(11 downto 0) = CSR_MIP then
+							v_output.result := "000000000000000000000000" & v_mtip & "0000000";
 						elsif input.operand2(11 downto 0) = CSR_MCYCLE then
 							v_output.result := mcycle;
 							v_mcycle := (mcycle or csr_set_bits) and csr_clear_bits;
 							else
 								-- trying to read non-existent CSR
 								has_exception := true;
+								v_mcause_code := EX_CAUSE_ILLEGAL_INSTRUCTION;
 							end if;
 						else
 							-- trying to write to non-existent or read-only CSR
 							has_exception := true;
+							v_mcause_code := EX_CAUSE_ILLEGAL_INSTRUCTION;
 						end if;
 					elsif input.operation = OP_MRET then
+						v_mstatus_mie := mstatus_mpie;
+						v_mstatus_mpie := '1';
 						v_jump := '1';
 						v_jump_address := mepc & "00";
 						-- TODO: reset mepc?
 					elsif input.operation = OP_ECALL then
 						has_exception := true;
+						v_mcause_code := EX_CAUSE_ENVIRONMENT_CALL;
 					elsif input.operation = OP_EBREAK then
 						has_exception := true;
+						v_mcause_code := EX_CAUSE_BREAKPOINT;
 					elsif input.operation = OP_LED then
 						led <= input.operand1(7 downto 0);
 					else
 					v_output.destination_reg := input.destination_reg;
 				end if;
+				if mstatus_mie = '1' and mtie = '1' and v_mtip = '1' then
+					has_exception := true;
+					v_mcause_int := '1';
+					v_mcause_code := INT_CAUSE_MACHINE_TIMER_INTERRUPT;
+				elsif v_jump = '1' and v_jump_address(1) /= '0' then
 					has_exception := true;
+					v_mcause_code := EX_CAUSE_INSTRUCTION_ADDRESS_MISALIGNED;
 				end if;
 				if has_exception then
 					v_minstret := v_minstret_inc;
 					v_minstreth := v_minstreth_inc;
 					v_mepc := input.pc(31 downto 2);
+					v_mtval := (others => '0');
+					v_mstatus_mie := '0';
+					v_mstatus_mpie := mstatus_mie;
+					v_mtie := mtie;
+					v_mtvec_address := mtvec_address;
+					v_mtvec_mode := mtvec_mode;
+					v_mscratch := mscratch;
+					v_mcause_int := mcause_int;
+					v_mcause_code := mcause_code;
 				end if;
 			end if;
 			mepc <= v_mepc;
 			mcause_int <= v_mcause_int;
 			mcause_code <= v_mcause_code;
+			mtval <= v_mtval;
+			mstatus_mie <= v_mstatus_mie;
+			mstatus_mpie <= v_mstatus_mpie;
+			mtie <= v_mtie;
+			mtvec_address <= v_mtvec_address;
+			mtvec_mode <= v_mtvec_mode;
+			mscratch <= v_mscratch;
+			mcause_int <= v_mcause_int;
+			mcause_code <= v_mcause_code;
 		end if;
 	end process;

...

src/core/execute.vhd CHANGED Viewed

@@ -41,8 +41,11 @@ architecture rtl of execute is
 	signal mtimeh: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimecmp: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimecmph: std_logic_vector(31 downto 0) := (others => '0');
 begin
 	process (clk)
 		variable v_output: execute_output_t;
 		variable v_sign: std_logic_vector(31 downto 0);
@@ -66,6 +69,7 @@ begin
 		variable v_mtvec_address: std_logic_vector(29 downto 0);
 		variable v_mtvec_mode: std_logic;
 		variable v_mscratch: std_logic_vector(31 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
@@ -389,8 +393,8 @@ begin
 							v_mepc := (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
 						elsif input.operand2(11 downto 0) = CSR_MCAUSE then
 							v_output.result := mcause_int & "000000000000000000000000000" & mcause_code;
-							mcause_int <= (mcause_int or csr_set_bits(31)) and csr_clear_bits(31);
-							mcause_code <= (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MTVAL then
 							v_output.result := mtval;
 							v_mtval := (mtval or csr_set_bits) and csr_clear_bits;
@@ -451,7 +455,7 @@ begin
 						has_exception := true;
 						v_mcause_code := EX_CAUSE_BREAKPOINT;
 					elsif input.operation = OP_LED then
-						led <= input.operand1(7 downto 0);
 					else
 						assert false report "Unhandled operation value in execute stage" severity failure;
 					end if;
@@ -492,6 +496,7 @@ begin
 					v_mscratch := mscratch;
 					v_mcause_int := mcause_int;
 					v_mcause_code := mcause_code;
 				end if;
 			end if;
@@ -519,6 +524,7 @@ begin
 			mscratch <= v_mscratch;
 			mcause_int <= v_mcause_int;
 			mcause_code <= v_mcause_code;
 		end if;
 	end process;

 	signal mtimeh: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimecmp: std_logic_vector(31 downto 0) := (others => '0');
 	signal mtimecmph: std_logic_vector(31 downto 0) := (others => '0');
+	signal s_led: std_logic_vector(7 downto 0) := (others => '0');
 begin
+	led <= s_led;
 	process (clk)
 		variable v_output: execute_output_t;
 		variable v_sign: std_logic_vector(31 downto 0);
 		variable v_mtvec_address: std_logic_vector(29 downto 0);
 		variable v_mtvec_mode: std_logic;
 		variable v_mscratch: std_logic_vector(31 downto 0);
+		variable v_led: std_logic_vector(7 downto 0);
 		variable v_address, v_value: std_logic_vector(31 downto 0);
 							v_mepc := (mepc or csr_set_bits(31 downto 2)) and csr_clear_bits(31 downto 2);
 						elsif input.operand2(11 downto 0) = CSR_MCAUSE then
 							v_output.result := mcause_int & "000000000000000000000000000" & mcause_code;
+							v_mcause_int := (mcause_int or csr_set_bits(31)) and csr_clear_bits(31);
+							v_mcause_code := (mcause_code or csr_set_bits(5 downto 0)) and csr_clear_bits(5 downto 0);
 						elsif input.operand2(11 downto 0) = CSR_MTVAL then
 							v_output.result := mtval;
 							v_mtval := (mtval or csr_set_bits) and csr_clear_bits;
 						has_exception := true;
 						v_mcause_code := EX_CAUSE_BREAKPOINT;
 					elsif input.operation = OP_LED then
+						v_led := input.operand1(7 downto 0);
 					else
 						assert false report "Unhandled operation value in execute stage" severity failure;
 					end if;
 					v_mscratch := mscratch;
 					v_mcause_int := mcause_int;
 					v_mcause_code := mcause_code;
+					v_led := s_led;
 				end if;
 			end if;
 			mscratch <= v_mscratch;
 			mcause_int <= v_mcause_int;
 			mcause_code <= v_mcause_code;
+			s_led <= v_led;
 		end if;
 	end process;

@@ -8,3 +8,6 @@ cpu.ip_user_files/
 cpu.sim/
 cpu.runs/
 cpu.srcs/

 cpu.sim/
 cpu.runs/
 cpu.srcs/
+toolchain/resources/output.elf
+toolchain/resources/output.bin

+.section .text
+.global _start
+_start:
+csrr x1, mvendorid

+#!/bin/env bash
+# exit if any command fails
+set -e
+# make a temporary directory
+tmp=$(mktemp -d)
+# assemble
+riscv-elf-as "$1" -o "$tmp/output.o"
+# link
+riscv-elf-ld "$tmp/output.o" -T resources/linker.ld -o resources/output.elf
+# extract binary
+riscv-elf-objcopy -O binary resources/output.elf resources/output.bin

@@ -1,5 +1,5 @@
 #include <stdint.h>
-#include <stdio.h>
 #define LENGTH 4484
 int16_t input[LENGTH] = { 17, 28, 8, -25, 33, -48, 2, 42, 39, -10, 29, -26, 24, 44, -37, -1, -4, 2, -43, -6, -44, 29, 47, -48, 13, -18, 18, 30, -44, 35, 18, 2, -38, 50, -28, 18, 21, 32, -8, 18, -33, 24, 46, -6, -9, 39, 7, 48, 41, -26, -52, 1, -1, -40, -60, 18, -18, -87, 73, -86, -45, 69, -24, -31, -69, -12, -79, 84, 83, 24, 70, -75, -81, -38, 24, 26, -26, -48, -52, -10, -90, 4, 54, -88, 31, -3, 91, -67, 65, -61, -32, 63, 83, -50, -90, 75, -26, -23, -26, -61, -89, -65, 250, 60, 652, -47, 88, 50, -61, -113, 36, 823, 26, -849, -46, 27, 58, 41, 68, -48, -42, 15, -22, 49, 78, 322, 28, -28, -95, -33, 56, -28, 37, 63, 13, -8, -57, 52, -64, -36, -8, -28, -313, 49, -87, -13, 24, 911, -35, -117, 60, -65, 34, -3, 52, 54, 85, -371, -67, -8, 668, -22, 96, 51, 8, -55, 69, 31, 83, -49, -734, 165, 35, 85, -45, 60, 332, 32, 36, -31, -22, 233, -702, 80, -23, 865, -6, -94, 57, 18, 225, 955, 34, -47, 55, -97, -9, 4, 63, 43, -1, 18, 7, 75, -224, -76, 10, 79, -898, -91, -47, -3, -74, 19, 50, -45, 46, 54, 36, 28, 8, -27, 55, 41, -41, 540, 60, 58, 76, -3, -831, -45, -78, -77, -2, -50, 24, -572, 3, -94, -509, -53, -35, 559, 21, -292, 10, 16, -98, 812, -40, 10, 74, 16, 255, 92, 670, -73, 56, -59, -41, -938, -62, -84, -5, 89, -23, 423, 62, -162, -57, -698, -80, 47, -413, -899, -69, 92, 322, -145, 59, 41, 39, -39, 9, -34, -28, -58, 559, -59, -89, -19, -13, 94, 34, 77, -2, -91, -86, -94, -67, -63, 430, -5, 5, 70, 30, -67, 67, -30, -39, -131, -21, 19, 98, -96, 36, 610, 54, -72, -90, -49, 11, -77, -93, -30, -5, 79, 67, 59, -29, 63, 66, -54, -546, -101, -28, 4, -6, 96, -1, 323, 435, -22, -74, -80, 54, 658, 88, -46, 21, -23, -89, -84, 72, 3, 60, 40, 48, -49, 1, -5, -195, 46, -20, 686, 88, -80, 50, 81, -31, -67, 15, -398, -269, -1, -722, -978, 53, -153, 39, 61, 7, 517, -24, -19, 19, 45, 135, 70, 950, 67, -267, -672, 41, 896, -65, -33, 35, 883, -72, -27, -86, -81, 81, -87, 13, 88, -48, 52, -47, -52, 117, -653, -36, -88, 12, -71, 25, 64, 751, -7, -33, 598, -98, 54, 30, 766, 15, -60, 695, -1, -56, 39, 16, -98, 101, 99, -277, -564, 41, -21, -79, -23, 777, 246, 37, 563, 40, 784, -80, 56, -69, -31, 3, 23, -331, -95, -563, 63, -5, -84, -48, 16, 84, -63, 78, -17, -61, -30, 3, 301, 26, 128, -988, -13, -14, 87, 15, 85, -61, 48, -587, 65, 72, 63, -754, 733, -79, 584, -81, 597, -94, -40, -66, -94, 94, 15, -15, 24, 67, 807, 82, 86, -66, 20, -41, 95, 26, 70, 430, -3, 3, -47, 31, -890, 513, -7, 61, 39, -75, 886, -97, 86, 60, 140, -87, 49, 46, 23, -4, 10, -276, -61, 24, 76, -59, -42, -530, -8, 56, -696, -83, -38, -290, 57, -39, 99, 71, 55, -381, 28, -75, -26, 22, 77, -4, -94, 68, -68, -246, 11, -65, -54, -46, -58, 56, -98, 94, -94, -429, 29, 867, 133, 41, 17, -58, -9, 920, -12, 1, -28, -72, 769, 31, 18, 82, 33, 518, -375, -78, -98, 92, -16, -44, 31, -51, 65, 40, -17, 52, -879, 3, 14, 382, 28, 38, 23, 539, 869, -46, -23, -87, -3, 790, 878, 563, -41, -67, 50, 20, 55, 42, -47, -44, -78, -675, 44, -578, -22, -821, 21, 28, 18, -682, 42, 52, 8, -66, -986, -80, -67, 6, -38, -80, -38, -85, -32, -17, 95, -3, 25, -19, 19, -56, 178, -22, 55, -355, -966, 810, -8, -388, -56, 485, 51, -28, -50, -79, -64, -32, -52, -323, 61, -322, -579, -37, 477, 508, 46, 972, -607, -919, -85, -521, 25, 49, 32, 23, 477, 71, 92, -54, -468, 59, -5, 294, -274, 20, 65, 287, 13, -856, -71, -344, 71, 77, -56, 90, 333, 56, -79, 4, 286, 89, -78, 20, 58, -313, 822, -5, 5, 92, 82, 17, 41, -38, 50, -71, -882, -75, 75, 298, -43, 45, 5, 21, 74, -55, 58, -36, 633, 57, 43, 15, -8, 93, 376, -781, 50, 55, -68, 56, -17, -71, 52, 435, 73, 69, -70, 97, 850, 44, -50, -8, 62, 18, -272, 15, 85, -14, 214, 46, -46, -51, 751, 37, 363, -18, -82, 288, -68, -94, -3, 2, 82, -21, 32, 82, -37, 37, -33, 81, 52, 51, 74, 75, -51, -44, 52, 43, 547, 753, 185, 78, 83, 54, -22, 25, -71, -32, -47, 60, 46, 80, -81, -35, 894, 14, 69, -54, 74, -24, -6, 5, -565, -30, -93, -7, 28, -85, -39, -63, 59, -30, -345, -674, 75, -354, -908, 622, 10, 4, -48, 55, -2, 99, -3, -1, -31, -54, 60, 3, 84, 40, 228, 92, -95, -177, -50, -71, 60, -38, 27, 75, 47, -126, 12, 287, 71, 95, -39, -9, 441, -92, -158, 36, 5, 49, 51, 877, -503, 241, -38, 74, 975, 49, -17, 19, -53, 53, 26, -41, -85, 22, 260, -7, -19, -70, -48, 270, 9, 71, -88, -87, 87, 2, 14, 84, -67, -33, -38, 75, -37, 13, -13, 43, -1, 51, 7, 63, -29, 15, -563, 58, -19, 50, -275, -10, 71, 42, -83, -20, -62, 88, -26, -99, -1, 93, -95, -36, -62, 29, -61, 43, 89, -10, 65, 781, 64, 84, 16, 76, 19, 98, -730, -63, 921, 83, -4, -16, -84, 77, -57, 91, 46, 89, -546, 17, 55, 51, -31, -92, -63, 47, 16, 20, 23, -43, 18, 20, -35, 97, 662, 28, 26, -16, -18, 88, 4, 29, -3, -53, 132, 21, -36, -59, 95, 15, -70, -80, 35, 66, -66, 63, 27, -358, 68, -23, 423, 62, -25, 63, -212, 12, 50, -27, 16, 23, 36, -98, -13, 85, 52, -302, 78, 398, -198, 96, -50, -46, 82, -129, -80, -13, 5, -73, -89, -58, -335, 25, 88, -164, -15, 61, 95, 69, 1, 30, 272, -221, -79, 165, 28, 43, 6, -96, 82, 82, -582, 18, 82, -637, -70, -93, -471, -633, -41, 97, -252, 59, 63, -38, 16, -41, 61, 80, 337, 94, 69, -58, 36, 15, 83, 924, 62, -48, -14, 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+    .section .text
+    .globl _start
+_start:
+    /* Clear mscratch (swap with zero) */
+    li      t0, 0
+    csrrw   t1, mscratch, t0     /* t1 = old mstatus, mstatus = 0 */
+    /* Set some bits using register variant */
+    li      t0, 0x8             /* example: set MIE bit */
+    csrrs   t2, mscratch, t0     /* set bits, t2 = old mstatus */
+    /* Clear some bits using register variant */
+    li      t0, 0x8
+    csrrc   t3, mscratch, t0     /* clear MIE bit, t3 = old mstatus */
+    /* Set bits using immediate variant */
+    csrsi   mscratch, 0x8        /* set MIE bit */
+    /* Clear bits using immediate variant */
+    csrci   mscratch, 0x8        /* clear MIE bit */
+    /* Read CSR using register variant (no side effects) */
+    csrrs   t4, mscratch, x0     /* t4 = mstatus */
+    /* Read CSR using immediate variant (no side effects) */
+    csrrsi  t5, mscratch, 0      /* t5 = mstatus */
+    /* Swap CSR and register again */
+    li      t0, 0x1800          /* example: set MPP=11 */
+    csrrw   t6, mscratch, t0     /* t6 = old mstatus */
+hang:
+    j       hang

+#!/usr/bin/env bash
+# compile and link
+riscv-elf-gcc -march=rv32i -mabi=ilp32 -nostdlib -ffreestanding -O3 resources/start.s "$1" -T resources/linker.ld -o resources/output.elf
+# extract binary
+riscv-elf-objcopy -O binary resources/output.elf resources/output.bin

@@ -1,5 +0,0 @@
-#!/usr/bin/env bash
-riscv-elf-gcc -march=rv32i -mabi=ilp32 -nostdlib -ffreestanding -O2 start.s main.c -T linker.ld -o prog.elf
-riscv-elf-objcopy -O binary prog.elf prog.bin
-python process.py


1	+ #!/bin/env bash
2	+
3	+ riscv-elf-objdump -D resources/output.elf -j .text -j .rodata -j .data -j .bss \| less -

@@ -1,24 +0,0 @@
-#!/usr/bin/env python
-SIZE=4096
-LINE=8
-DEFAULTWORD = 'X"00000000"'
-data=[]
-inputdata = open('prog.bin','rb').read()
-pad = (-len(inputdata)) % 4
-inputdata += b'\x00' * pad
-for i in range(0, len(inputdata), 4):
-    w = inputdata[i:i+4]
-    val = int.from_bytes(w, 'little')
-    data.append(f'X"{val:08x}"')
-oldsize = len(data)
-for i in range(oldsize, SIZE):
-    data.append(DEFAULTWORD)
-i = 0
-while i < SIZE:
-    print(', '.join(data[i:i+LINE]) + ('' if i + LINE >= len(data) else ','))
-    i += LINE

+#!/bin/env python3
+BINARY_FILE_PATH = 'resources/output.bin'
+WORDS_PER_LINE = 8
+LOGSIZE2 = 14
+SOURCE_FILE_PATH = '../src/bram.vhd'
+START_MARKER = '-- START PROGMEM'
+END_MARKER = '-- END PROGMEM'
+MEMORY_SIZE = 1 << LOGSIZE2
+WORDS_LEN = 1 << (LOGSIZE2 - 2)
+# load binary to buffer
+buffer = [0] * WORDS_LEN
+with open(BINARY_FILE_PATH, 'rb') as f:
+	i = 0
+	j = 0
+	while True:
+		word = f.read(4)
+		if not word:
+			break
+		if len(word) < 4:
+			raise ValueError(f"Incomplete 32-bit word at offset {i}")
+		buffer[j] = int.from_bytes(word)
+		i += 4
+		j += 1
+i = 0
+lines = ['\ttype ram_type is array (0 to 4095) of std_logic_vector(31 downto 0);', '\tshared variable RAM: ram_type := (']
+while i < WORDS_LEN:
+	lines.append('\t\t' + ', '.join(map(lambda x: f'X"{x:08x}"', buffer[i:i+WORDS_PER_LINE]))
+	   + (',' if (i + WORDS_PER_LINE) < WORDS_LEN else ''))
+	i += WORDS_PER_LINE
+lines.append('\t);')
+# put the binary in the source file
+text = [line.rstrip("\n") for line in open(SOURCE_FILE_PATH)]
+start_idx, end_idx = text.index(START_MARKER), text.index(END_MARKER)
+assert 0 < start_idx and start_idx < end_idx
+open(SOURCE_FILE_PATH, 'w').write('\n'.join(text[0 : start_idx + 1] + lines + text[end_idx :]))

@@ -9,4 +9,3 @@ SECTIONS {
   .data : { *(.data*) }
   .bss  : { *(.bss*)  }
 }

@@ -1,8 +0,0 @@
-    .section .text,"ax",@progbits
-    .global _start
-    .type _start, @function
-_start:
-    call main
-    .p2align 2
-    .word 0x0000006f

	@@ -0,0 +1,35 @@

	@@ -0,0 +1,6 @@

	@@ -0,0 +1,16 @@

	@@ -0,0 +1,7 @@